State the classifications of FET devices.

1 Answer

Answer :

FET is classified as  
 1. Junction Field Effect Transistor (JFET)  
 2. Metal oxide semiconductor family (MOS).

Related questions

Description : What are the classifications of sequential circuits?

Last Answer : The sequential circuits are classified on the basis of timing of their signals into two types. They are, 1) Synchronous sequential circuit. 2) Asynchronous sequential circuit.

Description : List basic types of programmable logic devices.

Last Answer : 1. . Read only memory 2. . Programmable logic Array 3. . Programmable Array Logic

Description : Explain the different methods of state assignment

Last Answer : • Three row state assignment • Shared row state assignment • Four row flow table • Multiple row state assignment • Prevention of races can happen only when S=0 and R=1.

Description : State with a neat example the method for the minimization of primitive flow table.

Last Answer : • Consider a state diagram • Obtain the flow table • Using implication table reduce the flow table • Using merger graph obtain maximal compatibles • Verify closed & covered conditions • Plot the reduced flow table

Description : Explain the working of BCD Ripple Counter with the help of state diagram and logic diagram.

Last Answer : • BCD Ripple Counter Count sequence • Truth Table • State diagram representing the Truth Table • Truth Table for the J-K Flip Flop • Logic Diagram

Description : State the types of ROM

Last Answer : 1. Masked ROM. 2. Programmable Read only Memory 3. Erasable Programmable Read only memory. 4. Electrically Erasable Programmable Read only Memory.

Description : What happens to output when a tri-state circuit is selected for high impedance.

Last Answer : Output is disconnected from rest of the circuits by internal circuitry.

Description : State advantages and disadvantages of TTL

Last Answer : Advantages: 1. Easily compatible with other ICs 2. Low output impedance

Description : How Scotty transistors are formed and state its use?

Last Answer : A Scotty diode is formed by the combination of metal and semiconductor. The presence of Scotty diode between the base and the collector prevents the transistor from going into saturation. ... of Scotty transistor in TTL decreases the propagation delay without a sacrifice of power dissipation.

Description : Explain in detail about Races.

Last Answer : • Basics of races • Problem created due to races • Classification of races • Remedy for races • cycles

Description : Design a asynchronous sequential circuit with 2 inputs T and C. The output attains a value of 1 when T = 1 & c moves from 1 to 0. Otherwise the output is 0

Last Answer : • Obtain the state diagram • Obtain the flow table • Using implication table reduce the flow table • Using merger graph obtain maximal compatibles • Verify closed & covered conditions • Plot the reduced flow table • Obtain transition table • Excitation table • Logic diagram

Description : Explain with neat diagram the different hazards and the way to eliminate them.

Last Answer : • Classification of hazards • Static hazard & Dynamic hazard definitions • K map for selected functions • Method of elimination • Essential hazards

Description : Explain in detail about serial in serial out shift register.

Last Answer : • Block diagram • Theoretical explanation • Logic diagram • Working

Description : Design a sequential detector which produces an output 1 every time the input sequence 1011 is detected.

Last Answer : • Construct state diagram • Obtain the flow table • Obtain the flow table & output table • Transition table • Select flip flop • Excitation table

Description : mplement W (A,B,C,D) = Ʃ (2,12,13)

Last Answer : X(A,B,C,D) = Ʃ (7,8,9,10,11,12,13,14,15) Y(A,B,C,D) = Ʃ (0,2,3,4,5,6,7,8,10,11,15) Z (A,B,C,D) = Ʃ (1,2,8,12,13) using PAL(16) • Table • PAL implementation

Description : Implement F(A,B,C,D)= Ʃ (1,3,4,11,12,13,14,15) using multiplexer

Last Answer : • Implementation • Table • Explanation

Description : Explain in detail about PLA and PAL.

Last Answer : • Logic difference between Prom & PLA • Logic diagram implementing a function • Logic difference between Prom & PAL • Logic diagram implementing a function

Description : Design a logic circuit to convert the BCD code to Excess –

Last Answer : code. • Truth Table for BCD to Excess – 3 conversion. • K-map simplification • Logic circuit implementing the Boolean Expression

Description : Explain in detail the look ahead carry generator.

Last Answer : • Block diagram • Explanation • Logic diagram

Description : Design and explain a comparator to compare two identical

Last Answer : words. • Two numbers represented by A = A3A2A1A0 & B = B3B2B1B0 • If two numbers equal P = Ai Bi • Obtain the logic Expression. • Obtain the logic diagram.

Description : Explain the flip-flop excitation tables for RS FF.

Last Answer : • RS flip-flop • In RS flip-flop there are four possible transitions from the present state to the next state. They are, • 0 0 transition: This can happen either when R=S=0 or when R=1 and S=0. • 0 1 transition: This can happen only when S=1 and R=0. • 1 0 transition: This

Description : What are the different types of shift type?

Last Answer : There are five types. They are, Serial In Serial Out Shift Register Serial In Parallel Out Shift Register Parallel In Serial Out Shift Register Parallel In Parallel Out Shift Register Bidirectional Shift Register

Description : Define shift registers.

Last Answer : Define shift registers.

Description : Define registers.

Last Answer : A register is a group of flip-flops flip-flop can store one bit information. So an n bit register has a group of n flip-flops and is capable of storing any binary information/number containing n-bits.

Description : Define propagation delay.

Last Answer : A propagation delay is the time required to change the output after the application of the input.

Description : Define hold time.

Last Answer : The hold time is the minimum time for which the voltage levels at the excitation inputs must remain constant after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as thold .

Description : Define setup time.

Last Answer : The setup time is the minimum time required to maintain a constant voltage levels at the excitation inputs of the flip-flop device prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as tsetup.

Description : Define skew and clock skew

Last Answer : The phase shift between the rectangular clock waveforms is referred to as skew and the time delay between the two clock pulses is called clock skew.

Description : Define fall time.

Last Answer : The time required to change the voltage level from 90% to 10% is known as fall time(tf).

Description : Define rise time.

Last Answer : The time required to change the voltage level from 10% to 90% is known as rise time(tr).

Description : What is a master-slave flip-flop?

Last Answer : A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.

Description : What is edge-triggered flip-flop?

Last Answer : The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock.

Description : Define race around condition.

Last Answer : In JK flip-flop output is fed back to the input. Therefore change in the output results change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called ‘race around condition’.

Description : What is the operation of T flip-flop?

Last Answer : T flip-flop is also known as Toggle flip-flop. • When T=0 there is no change in the output. • When T=1 t

Description : What is the operation of JK flip-flop?

Last Answer : When K input is low and J input is high the Q output of flip-flop is set. When K input is high and J input is low the Q output of flip-flop is reset. When both the inputs K and ... are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.

Description : What is the operation of D flip-flop?

Last Answer : In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.

Description : What are the different types of flip-flop?

Last Answer : There are various types of flip flops. Some of them are mentioned below they are, 1. RS flip-flop 2. SR flip-flop 3. D flip-flop 4. JK flip-flop 5. T flip-flop

Description : Define Flip flop.

Last Answer : The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state.

Description : Give the comparison between PROM and PLA.

Last Answer : PROM PLA 1. And array is fixed and OR Both AND and OR arrays are array is programmable. Programmable. 2. Cheaper and simple to use. Costliest and complex than PROMS.

Description : What does PAL 10L8 specify?

Last Answer : PAL - Programmable Logic Array 10 - Ten inputs L - Active LOW Output 8 - Eight Outputs

Description : Why the input variables to a PAL are buffered

Last Answer : The input variables to a PAL are buffered to prevent loading by the large number of AND gate inputs to which available or its complement can be connected.

Description : Why was PAL developed?

Last Answer : It is a PLD that was developed to overcome certain disadvantages of PLA, such as longer delays due to additional fusible links that result from using two programmable arrays and more circuit complexity.

Description : Define PROM.

Last Answer : PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates connected to a decoder and a programmable OR array.

Description : Define PLD.Give the classification of PLDs.

Last Answer : PLDs are classified as PROM (Programmable Read Only Memory), Programmable Logic Array (PLA), Programmable Array Logic (PAL), and Generic Array Logic (GAL)

Description : List the major differences between PLA and PA

Last Answer : PLA: Both AND and OR arrays are programmable and Complex, Costlier than PAL PAL AND arrays are programmable OR arrays are fixed, Cheaper and Simpler

Description : What is field programmable logic array?

Last Answer : The second type of PLA is called a field programmable logic array. The user by means of certain recommended procedures can program the EPLA.

Description : What is mask - programmable?

Last Answer : With a mask programmable PLA, the user must submit a PLA program table to the manufacturer.

Description : What is programmable logic array? How it differs from ROM?

Last Answer : In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the min-terms as in the ROM.

Description : What is RAM?

Last Answer : Random Access Memory. Read and write operations can be carried out.

Description : Explain EEPROM.

Last Answer : EEPROM (Electrically Erasable Programmable Read Only Memory) EEPROM also use MOS circuitry. Data is stored as charge or no charge on an insulated layer or an insulated floating gate in ... rather than erasing all the information since the information can be changed by using electrical signals.