Description : Pipeline implement a. fetch instruction b. decode instruction c. fetch operand d. calculate operand e. execute instruction f. all of abve
Last Answer : f. all of abve
Description : A compiler is a translating program which a. Translates instruction of a high level language into machine language b. Translates entire source program into machine language program c. It is not involved in program’s execution d. All of above
Last Answer : d. All of above
Description : The ____ of can assembly line to be I/t p: a. Clock period b. Pipelining c. Throughput d. Flow through
Last Answer : c. Throughput
Description : The fetch-execute cycle is to use a system know as: a. Assembly line b. Pipelining c. Cache d. None of these
Last Answer : b. Pipelining
Description : Who is the represents the fundamental process in the operation of the CPU: a. The fetch-execute cycle and pipelining b. The assembly c. Both A and B d. None of these
Last Answer : a. The fetch-execute cycle and pipelining
Description : How can we make computers work faster? a. The fetch-execute cycle and pipelining b. The assembly c. Both A and B d. None of these
Description : In 8086 microprocessor one of the following statements is not true.a)Coprocessor is interfaced in MAX mode b)Coprocessor is interfaced in MIN mode c)I/O can be interfaced in MAX / MIN moded)Supports pipelining
Last Answer : b)Coprocessor is interfaced in MIN mode
Description : If ______input pin of 80386 if activated, allows address pipelining during 80386 bus cycles. a) BS16 b) NA c) PEREQ d) ADS
Last Answer : a) BS16
Description : Define pipelining.
Last Answer : Pipelining: Process of fetching the next instruction while the current instruction is executing is called pipelining which will reduce the execution time.
Description : The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Fully decoding b. Half decoding c. Both a & b d. None of these
Last Answer : a. Fully decoding
Description : Which statement is wrong according to linear decoding : a. Address map is not contiguous. b. Confects occur if two of the select lines become active at the same time c. If all unused address lines are not used as chip selectors then these unused lines become don’t cares d. None of these
Last Answer : d. None of these
Description : In linear decoding address bus of 16-bit wide can connect only ____ of RAM. a. 16 KB b. 6KB c. 12KB d. 64KB
Last Answer : b. 6KB
Description : Which storage technique dose not decoding circuit: a. Linear decoding b. Fully decoding c. Partially d. None of these
Last Answer : a. Linear decoding
Description : Which technique is used for main memory array design: a. Linear decoding b. Fully decoding c. Both A and B d. None of these
Last Answer : c. Both A and B
Description : The work of EU is ________ A. encoding B. decoding C. processing D. calculations
Last Answer : The work of EU is decoding
Description : Which of the following processor architecture supports easier instruction pipelining? A. Harvard B. Von Neumann C. Both of them D. None of these
Last Answer : A. Harvard
Description : Pipelining improves performance by: (A) decreasing instruction latency (B) eliminating data hazards (C) exploiting instruction level parallelism (D) decreasing the cache miss rate
Last Answer : (C) exploiting instruction level parallelism
Description : A modern electronic computer is a machine that is meant for a. Doing quick mathematical calculations b. Input, storage, manipulation and outputting of data c. Electronic data processing d. Performing repetitive tasks accurately
Last Answer : b. Input, storage, manipulation and outputting of data
Description : Opcode is the machine instruction obtained from decoding instruction stored in. a. Stack pointer b. Address pointer Cc. Instruction register d. Incrementer
Last Answer : Cc. Instruction register
Description : Decoding of an instruction in RISC architecture means decision on working of control unit for: a. Remainder of instructions b. _ Divisor of instructions c. Dividend of instructions d. None of these
Last Answer : a. Remainder
Description : The minimum number of transistors required to implement a two input AND gate is a. 2 b. 4 c. 6 d. 8
Last Answer : c. 6
Description : A stack is a. an 8-bit register in the microprocessor b. a 16-bit register in the microprocessor c. a set of memory locations in R/WM reserved for storing information temporarily during the execution of computer
Last Answer : c. a set of memory locations in R/WM reserved for storing information temporarily during the execution of computer
Description : Time during which a job is processed by the computer is a. Delay times b. Real time c. Execution time d. Down time
Last Answer : b. Real time
Description : 80386 support overall ___ addressing modes to facilitate efficient execution of higher level language programs. a) 9 b) 10 c) 11 d) 12
Last Answer : 11
Description : Why 8087 is referred to as Coprocessor? i) Because 8087 is used in parallel with main processor in a system, rather than serving as a main processor itself. ii) Because 8087 is used in serial with main processor in a ... math computations. a) i & iii b) ii & iii c) iii only. d) i only.
Last Answer : c) iii only.
Description : When a subroutine is called, the address of the instruction following the CALL instructions stored in/on the a. stack pointer b. accumulator c. program counter d. stack
Last Answer : d. stack
Description : In data transfer manipulation designing as instruction set for a system isa complex_ a. Art b. System Cc. Computer d. None of these
Last Answer : a. Art
Description : Which is data manipulation types are. a. Arithmetic instruction b. Shift instruction c. Logical and bit manipulation instructions d. All of these
Last Answer : d. All of these
Description : In which instruction are used to perform Boolean operation on non-numerical data: a. Logical and bit manipulation b. Shift manipulation c. Circular manipulation d. None of these
Last Answer : a. Logical and bit manipulation
Description : Who change the address in the program counter and cause the flow of control to be altered: a Shift manipulation b. Circular manipulation c. Program control instruction d. __ Allof these
Last Answer : c. Program control instruction
Description : How does the microprocessor differentiate between data and instruction
Last Answer : When the first m/c code of an instruction is fetched and decoded in the instruction register, the microprocessor recognizes the number of bytes required to fetch the entire ... will be considered as data & the byte after the data will be treated as the next instruction.
Description : Why do we use XRA A instruction
Last Answer : The XRA A instruction is used to clear the contents of the Accumulator and store the value 00H.
Description : Explain the different instruction formats with examples
Last Answer : The instruction set is grouped into the following formats • One byte instruction MOV C,A • Two byte instruction MVI A,39H • Three byte instruction JMP 2345H
Description : Mention the categories of instruction and give two examples for each category
Last Answer : The instructions of 8085 can be categorized into the following five • Data transfer MOV Rd,Rs STA 16-bit • Arithmetic ADD R DCR M • Logical XRI 8-bit RAR • Branching JNZ CALL 16-bit • Machine control HLT NOP
Description : What is an instruction?
Last Answer : An instruction is a binary pattern entered through an input device to command the microprocessor to perform that specific function
Description : Define instruction cycle, machine cycle and T-state
Last Answer : Instruction cycle is defined, as the time required completing theexecution of an instruction. Machine cycle is defined as the time required completing one operation of accessing memory, I/O or ... request. Tcycle is defined as one subdivision of the operation performed in one clock period
Description : Explain the difference between a JMP instruction and CALL instruction.
Last Answer : A JMP instruction permanently changes the program counter. A CALL instruction leaves information on the stack so that the original program execution sequence can be resumed.
Description : How many operations are there in the instruction set of 8085 microprocessor?
Last Answer : There are 74 operations in the 8085 microprocessor.
Description : CISC stands for: a. Complex instruction set computer b. Camper instruct set of computer c. Compared instruction set computer d. None of these
Last Answer : a. Complex instruction set computer
Description : RISC stands for: a. Reduced Instruction set computer b. Reduced Instruct set compare c. Reduced instruction stands computer d. All of these 107. DEC stands for:
Last Answer : a. Reduced Instruction set computer
Description : ISA stands for: a. Instruct set area b. Instruction set architecture c. Both a and b d. None of these
Last Answer : b. Instruction set architecture
Description : Which is not the main feature of DEC Alpha: a. 64 Bit RISC processor b. Designed to replace 32 VAX(CISC) c. Seven stage split integer/floating point pipeline d. Variable Instruction length
Last Answer : d. Variable Instruction length
Description : How many speed of 8088,8085,8086 microprocessor: a. 2.5 Million instruction per second b. 1.5 Million instruction per second c. 3.5 Million instruction per second d. 1.6 Million instruction per second
Last Answer : a. 2.5 Million instruction per second
Description : Which is most commonly measured in terms of MIPS previously million instruction per second: a. Microprocessor b. Performance of a microprocessor c. Assembly line d. None of thes
Last Answer : b. Performance of a microprocessor
Description : RISC stands for: a. Reduced Instruction Set Computer b. Reduced Intergraded Set Computer c. Resource Instruction Set Computer d. Resource Instruction System Computer
Last Answer : a. Reduced Instruction Set Computer
Description : CISC stands for: a. Complex Instruction System Computer b. Complex Instruction Set Car c. Complex Instruction Set Computer d. None of these
Last Answer : c. Complex Instruction Set Computer
Description : When the RET instruction at the end of subroutine is executed, a. the information where the stack is iniatialized is transferred to the stack pointer b. the memory address of the RET instruction is ... two data bytes stored in the top two locations of the stack are transferred to the stack pointer
Last Answer : c. two data bytes stored in the top two locations of the stack are transferred to the program counter
Description : In immediate addressing the operand is placed a. in the CPU register b. after OP code in the instruction c. in memory d. in stack
Last Answer : b. after OP code in the instruction
Description : Interrupts which are initiated by an instruction are a. internal b. external c. hardware d. software
Last Answer : b. external
Description : What is the control unit's function in the CPU? a. To transfer data to primary storage b. to store program instruction c. to perform logic operations d. to decode program instruction
Last Answer : b. to store program instruction