The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is? a) Exceptions b) Signal handling c) Interrupts d) DMA

Question

The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is? a) Exceptions b) Signal handling c) Interrupts d) DMA

The method of synchronising the processor
with the I/O device in which the device sends
a signal when it is ready is?
a) Exceptions
b) Signal handling
c) Interrupts
d) DMA

asked Oct 14, 2021 by aditya2321

1 Answer

Related questions

The method which offers higher speeds of I/O transfers is ___________ a) Interrupts b) Memory mapping c) Program-controlled I/O d) DMA

Description : The method which offers higher speeds of I/O transfers is ___________ a) Interrupts b) Memory mapping c) Program-controlled I/O d) DMA

Last Answer : DMA

To overcome the lag in the operating speeds of the I/O device and the processor we use ___________ a) BUffer spaces b) Status flags c) Interrupt signals d) Exceptions

Description : To overcome the lag in the operating speeds of the I/O device and the processor we use ___________ a) BUffer spaces b) Status flags c) Interrupt signals d) Exceptions

Last Answer : Status flags

Which are benefit of input/output interrupt: a. It is an external analogy to exceptions b. The processor initiates and perform all I/O operation c. The data is transferred into the memory through interrupt handler d. = Alllof these

Description : Which are benefit of input/output interrupt: a. It is an external analogy to exceptions b. The processor initiates and perform all I/O operation c. The data is transferred into the memory through interrupt handler d. = Alllof these

Last Answer : d. = Alllof these

BHE of 8086 microprocessor signal is used to interface the a) Even bank memory b) Odd bank memory c) I/O d) DMA

Description : BHE of 8086 microprocessor signal is used to interface the a) Even bank memory b) Odd bank memory c) I/O d) DMA

Last Answer : b) Odd bank memory

The DMA controllers are special hardware embedded into the chip in modern integrate processor that ____and_____ to the system; a. Data transfer b. arbitrate access c. Both A and B d. None of these

Description : The DMA controllers are special hardware embedded into the chip in modern integrate processor that ____and_____ to the system; a. Data transfer b. arbitrate access c. Both A and B d. None of these

Last Answer : c. Both A and B

What is true about SSO? A. SSO has multiple authentication server B. SSO managing single accesses to other systems C. In SSO, User sends the ticket to intranet server. D. All of the above

Description : What is true about SSO? A. SSO has multiple authentication server B. SSO managing single accesses to other systems C. In SSO, User sends the ticket to intranet server. D. All of the above

Last Answer : In SSO, User sends the ticket to intranet server.

Which of the following google product sends you periodic email alerts based on your search term? a) Alerts b) Blogger c) Calendar d) All of the mentioned

Description : Which of the following google product sends you periodic email alerts based on your search term? a) Alerts b) Blogger c) Calendar d) All of the mentioned

Last Answer : Alerts

To read a file in HDFS, a user sends an _______ request to the NameNode toget the location of file blocks. a) access b) open c) authentication d) create

Description : To read a file in HDFS, a user sends an _______ request to the NameNode toget the location of file blocks. a) access b) open c) authentication d) create

Last Answer : open

Which of the following google product sends you periodic email alerts based on your search term? a) Alerts b) Blogger c) Calendar d) All of the mentioned

Description : Which of the following google product sends you periodic email alerts based on your search term? a) Alerts b) Blogger c) Calendar d) All of the mentioned

Last Answer : Alerts

What are various interrupts supported by TMS 320 c54 processor?

Description : What are various interrupts supported by TMS 320 c54 processor?

Last Answer : The C54x DSP supports both software and hardware interrupts: ✔ A software interruptis requested by a program instruction (INTR, TRAP,or RESET) ✔ A hardware interrupt is requested by a ... interrupt ports. ✔ Internal hardware interrupts are triggered by signals from the on-chip peripherals.

There are three processes P1, P2 and P3 sharing a semaphore for synchronising a variable. Initial value of semaphore is one. Assume that negative value of semaphore tells us how many processes are waiting in queue. Processes access the semaphore in following order: (a) P2 needs to access (b) P1 needs to access (c) P3 needs to access (d) P2 exits critical section (e) Pi exits critical section The final value of semaphore will be: (1) 0 (2) 1 (3) -1 (4) -2

Description : There are three processes P1, P2 and P3 sharing a semaphore for synchronising a variable. Initial value of semaphore is one. Assume that negative value of semaphore tells us how many processes are waiting in queue. Processes access ... The final value of semaphore will be: (1) 0 (2) 1 (3) -1 (4) -2

Last Answer : Answer: 1

The CPU completes yields control of the bus to the DMA controller via: a. DMA acknowledge signal b. DMA integrated signal c. DMA implicitly signal d. None of these

Description : The CPU completes yields control of the bus to the DMA controller via: a. DMA acknowledge signal b. DMA integrated signal c. DMA implicitly signal d. None of these

Last Answer : a. DMA acknowledge signal

Which of the following is open and both hypervisor and processor-architecture- agnostic? a) Dell Scalent b) CloudKick c) Elastra d) All of the mentioned

Description : Which of the following is open and both hypervisor and processor-architecture- agnostic? a) Dell Scalent b) CloudKick c) Elastra d) All of the mentioned

Last Answer : Dell Scalent

The process wherein the processor constantly checks the status flags is called as ___________ a) Polling b) Inspection c) Reviewing d) Echoing

Description : The process wherein the processor constantly checks the status flags is called as ___________ a) Polling b) Inspection c) Reviewing d) Echoing

Last Answer : Polling

In distributed system, each processor has its own ___________ a) local memory b) clock c) both local memory and clock d) none of the mentioned

Description : In distributed system, each processor has its own ___________ a) local memory b) clock c) both local memory and clock d) none of the mentioned

Last Answer : both local memory and clock

A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer? (A) 0.06% (B) 0.12% (C) 1.2% (D) 2.5%

Description : A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average ... of the DMA transfer? (A) 0.06% (B) 0.12% (C) 1.2% (D) 2.5%

Last Answer : Answer: B

The method of accessing the I/O devices by repeatedly checking the status flags is ___________ a) Program-controlled I/O b) Memory-mapped I/O c) I/O mapped CSE-R17.BLOGSPOT.COM d) None of the mentioned

Description : The method of accessing the I/O devices by repeatedly checking the status flags is ___________ a) Program-controlled I/O b) Memory-mapped I/O c) I/O mapped CSE-R17.BLOGSPOT.COM d) None of the mentioned

Last Answer : Program-controlled I/O

An interface that provides I/O transfer of data directly to and form the memory unit and peripheral is termed as________ A. DDA B. Serial interface C. Direct Memory Access (DMA) D. None of the Above

Description : An interface that provides I/O transfer of data directly to and form the memory unit and peripheral is termed as________ A. DDA B. Serial interface C. Direct Memory Access (DMA) D. None of the Above

Last Answer : C. Direct Memory Access (DMA)

Point out how DMA can improve I/O speed.

Description : Point out how DMA can improve I/O speed.

Last Answer : DMA is implemented with a specialized controller that transfers data between an I/O device and memory independent of the processor The DMA controller becomes the master and directs the reads and writes between itself and memory. During data transfer is not routed through the processors

Point out the wrong statement. CSE-R17.BLOGSPOT.COM a) SOA provides the standards that transportthe messages and makes the infrastructure to support it possible b) SOA provides access to reusable Web services over an SMTP network c) SOA offers access to ready-made, modular, highly optimized, and widely shareable components that can minimize developer and infrastructure costs d) None of the mentioned

Description : Point out the wrong statement. CSE-R17.BLOGSPOT.COM a) SOA provides the standards that transport the messages and makes the infrastructure to support it possible b) SOA provides access ... and widely shareable components that can minimize developer and infrastructure costs d) None of the mentioned

Last Answer : SOA provides access to reusable Web services over an SMTP network

Point out the wrong statement. a) SOA provides the standards that transport the messages and makes the infrastructure to support it possible b) SOA provides access to reusable Web services over an SMTP network c) SOA offers access to ready-made, modular, highly optimized, and widely shareable components that can minimize developer and infrastructure costs d) None of the mentioned

Description : Point out the wrong statement. a) SOA provides the standards that transport the messages and makes the infrastructure to support it possible b) SOA provides access to reusable Web services ... widely shareable components that can minimize developer and infrastructure costs d) None of the mentioned

Last Answer : SOA provides access to reusable Web services over an SMTP network

Which is one of the important I/O devices and is most commonly used as permanent storage device in any processor: a. Soft disk b. Hard disk c. Botha &b d. None of these

Description : Which is one of the important I/O devices and is most commonly used as permanent storage device in any processor: a. Soft disk b. Hard disk c. Botha &b d. None of these

Last Answer : b. Hard disk

Which are the functioning of I/O interrupt: a. The processor organizes all the I/O operation for smooth functioning b. After completing the I/O operation the device interrupt the processor c. Both d. None of these

Description : Which are the functioning of I/O interrupt: a. The processor organizes all the I/O operation for smooth functioning b. After completing the I/O operation the device interrupt the processor c. Both d. None of these

Last Answer : b. After completing the I/O operation the device interrupt the processor

The microprocessor can read/write 16 bit data from or to ________ A. memory B. I /O device C. processor D. register

Description : The microprocessor can read/write 16 bit data from or to ________ A. memory B. I /O device C. processor D. register

Last Answer : The microprocessor can read/write 16 bit data from or to memory

Interrupts which are initiated by an I/O drive are ___________ A. internal B. external C. Both (A) and (B) D. All of the above

Description : Interrupts which are initiated by an I/O drive are ___________ A. internal B. external C. Both (A) and (B) D. All of the above

Last Answer : B. external

Interrupts which are initiated by an I/O drive are a. internal b. external c. software d. all of above

Description : Interrupts which are initiated by an I/O drive are a. internal b. external c. software d. all of above

Last Answer : b. external

Which of the following is not the function of Microkernel? A) File management B) Low-level memory management C) Inter-process communication D) I/O interrupts management

Description : Which of the following is not the function of Microkernel? A) File management B) Low-level memory management C) Inter-process communication D) I/O interrupts management

Last Answer : A) File management

The essential difference between traps and interrupts is (A) traps are asynchronous and interrupts are synchronous with the program (B) traps are synchronous and interrupts are asynchronous with the program (C) traps are synchronous and interrupts are asynchronous with the I/O devices. (D) None of these.

Description : The essential difference between traps and interrupts is (A) traps are asynchronous and interrupts are synchronous with the program (B) traps are synchronous and interrupts are asynchronous with the program ( ... synchronous and interrupts are asynchronous with the I/O devices. (D) None of these.

Last Answer : (B) traps are synchronous and interrupts are asynchronous with the program

The system is notified of a read or write operation by ___________ a) Appending an extra bit of the address b) Enabling the read or write bits of the devices c) Raising an appropriate interrupt signal d) Sending a special signal along the BUS

Description : The system is notified of a read or write operation by ___________ a) Appending an extra bit of the address b) Enabling the read or write bits of the devices c) Raising an appropriate interrupt signal d) Sending a special signal along the BUS

Last Answer : Sending a special signal along the BUS

___________ acts as the nerve centre that sends control signal to all other units. -Technology

Description : ___________ acts as the nerve centre that sends control signal to all other units. -Technology

Last Answer : Control Unitacts as the nerve centre that sends control signal to all other units.

What Bonds to a molecule and sends signal to the inside of cell?

Description : What Bonds to a molecule and sends signal to the inside of cell?

Last Answer : Need answer

The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B

Description : The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B

Last Answer : b. Write

Which of the following is a push mechanism for publishing Web site data that is device- specific? A. WAP B. GPRS C. Bluetooth D. GAP

Description : Which of the following is a push mechanism for publishing Web site data that is device- specific? A. WAP B. GPRS C. Bluetooth D. GAP

Last Answer : WAP

Which of the following use LUNs to define a storage volume that appears to a connected computer as a device? a) SAN b) iSCSI c) Fibre Channel CSE-R17.BLOGSPOT.COM d) All of the mentioned

Description : Which of the following use LUNs to define a storage volume that appears to a connected computer as a device? a) SAN b) iSCSI c) Fibre Channel CSE-R17.BLOGSPOT.COM d) All of the mentioned