Question

Explain fabrication using N-well process.

Answer 1

N-Well process: The N-well CMOS circuits are getting more popular because of the lower substrate bias effect on transistor threshold voltage and lower parasitic capacitances associated with source and drain regions. 

The fabrication steps are as follows: 

Thick SiO₂ layer is grown on p-type silicon wafer. 

After defining the area for N-well diffusion, using a mask, the SiO₂ layer is etched off and n-well diffusion process is carried out. 

Oxide in the n transistor region is removed and thin oxide layer is grown all over the surface to insulate gate and substrate. 

The polysilicon is deposited and patterned on thin oxide regions using a mask to form gate of both the transistors. The thin oxide on source and drain regions of both the transistors is removed by proper masking steps. 

Using n+ mask and complementary n+ mask, source and drain of both nMOS and pMOS transistors are formed one after another using respective diffusion processes. These same masks also include the VDD and VSS contacts. 

The contacts are made using proper masking procedure and metal is deposited and patterned on the entire chip surface. 

An overall passivation layer is formed and the openings for accessing bonding pads are defined.