Compare signals and variables in VHDL
Sr. No
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Signals
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Variables
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1 |
Signal objects are used to connect entities together to form model
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Variables are used for local storage in process statements and subprograms.
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2 |
Signals have their values scheduled in the future
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Variables have all assignments to variables occur immediately
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3 |
The keyword signal is followed by one or more signal names
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The keyword variable is followed by one or more variable names
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4 |
Signals can be declared in entity declaration sections architecture declarations and package declarations
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Variables can be declared in the process declaration and subprogram declaration sections only.
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5 |
Signals need more information so more memory
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Variables take less memory
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