The simplest method of controlling sequence of instruction execution is to have each instruction explicitly
specify:

a. The address of next instruction to be run
b. Address of previous instruction
c. Both a &b
d. None of these

1 Answer

Answer :

a. The address of next instruction to be run

Related questions

Description : Execution of instruction specified by instruction to perform: a. Operation b. Operands c. Both a &b d. None of these

Last Answer : a. Operation

Description : The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, ... incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next

Last Answer : c. Instruction register, incremented and next

Description : An instruction code must specify the address of the__. a. Opecode b. Operand c. Both d. None

Last Answer : b. Operand

Description : Each instruction is executed by set of micro operations termed as. a. Micro instructions b. Mini instructions c. Botha &b d. None of these

Last Answer : a. Micro instructions

Description : When subroutine is called contents of program counter is location address of __ instruction following call instruction is stored on _ __and program execution is transferred to __ address. a. Non ... , Stack and Main program Cc. Executable, Queue and Subroutine d. Executable, Stack and Subroutine

Last Answer : d. Executable, Stack and Subroutine

Description : Which microinstruction provide next instruction from control memory: a. Microinstruction execution b. Microinstruction Buffer c. Microinstruction decoder d. Microinstraction Sequencing

Last Answer : d. Microinstraction Sequencing

Description : Modern assemblers for RISC based architectures make optimization of instruction scheduling to make use of CPU __ efficiently: a. Pipeline b. Without pipeline c. Botha &b d. None of these

Last Answer : a. Pipeline

Description : Return instruction is written in_ to written to main program: a. Subroutine b. Main program c. Botha &b d. None of these

Last Answer : a. Subroutine

Description : Which is the method by which instructions are selected for execution: a. Instruction selection b. — Selection control c. Instraction sequencing d. All of these

Last Answer : c. Instraction sequencing

Description : address is not assigned by linker. a. Absolute b. Relative c. Botha &b a None of these

Last Answer : a. Absolute

Description : shave addresses where instructions are stored along with address of working storage: a. _ Relative entities b. Absolute entities c. Botha &b d. None of these

Last Answer : a. _ Relative entities

Description : Which unit is necessary for the execution of instruction: a. Timing b. Control ce. Both d. None of these

Last Answer : ce. Both

Description : Micro-orders generate the_ __ address of operand and execute instruction and prepare for fetching next instruction from the main memory: a. Physical b. Effective c. Logical d. all of above

Last Answer : b. Effective

Description : The contents of the program counter isthe __——__—oof the instruction to be run. a. Data b. Address c. Counter d. None of these

Last Answer : b. Address

Description : The time required to complete one instruction is called. a. Fetch time b. Execution time c. Control time d. All of these

Last Answer : b. Execution time

Description : Which of the following 2 task are performed to execute an instruction by MCU: a. Microinstruction execution b. Microinstruction sequencing c. Botha&b d. None of these

Last Answer : c. Botha&b

Description : Copy of instruction in cache memory is known as: a Execution cache b. Data cache c. Instruction cache d. Allof these

Last Answer : c. Instruction cache

Description : state keeps track of position related to execution of an instruction: a. Major b. Minor c. Botha & b d. None of these

Last Answer : a. Major

Description : In protocol each process can make a request onlyinan a. Increasing order b. Decreasing order c. Botha &b d. None of these

Last Answer : a. Increasing order

Description : Which section is basically a sequence of instruction with a clear indication of beginning and end for updating shared variables. a. Racing section b. Critical section c. d. Both None of thes

Last Answer : . Critical sectio

Description : Which instruction are arranged as per the protocols of memory reference format of the input file in a simple ASCII sequence of integers between the range O to 99 separated by spaces without formatted text ... : a. Memory reference instruction b. Memory reference format c. Both d. None of these

Last Answer : a. Memory reference instruction

Description : is an external hardware event which causes the CPU to interrupt the current instruction sequence: a. Input interrupt b. Output interrupt c. Both d. None of these

Last Answer : c. Both

Description : In instruction formats instruction is represent by a___ _ of bits: a. Sequence b. Parallel c. Both d. None

Last Answer : a. Sequence

Description : In program control the instruction is set for the statement in a: a. Parallel b. Sequence c. Both d. None

Last Answer : b. Sequence

Description : In length instruction some programs wants a complex instruction set containing more instruction, more addressing modes and greater address rang, as in case of a. RISC b. CISC c. Both d. None

Last Answer : b. CISC

Description : Copy of data in cache memory is called. a. Datacache b. Execution cache c. Address cache d. Control cache

Last Answer : a. Datacache

Description : __is the sequence of operations performed by CPU in processing an instruction: a. Execute cycle b. Fetch cycle c. Decode d. Instruction cycle

Last Answer : d. Instruction cycle

Description : __is divided into a number of fields and is represented as a sequence of bits: a. instruction b. — instruction set c. instruction code d. parity code

Last Answer : a. instruction

Description : Which state refers to a state that is not safe not necessarily a deadlocked state. a. Safe state b. Unsafe state c. Botha &b d. None of these

Last Answer : b. Unsafe state

Description : Which is one of the important I/O devices and is most commonly used as permanent storage device in any processor: a. Soft disk b. Hard disk c. Botha &b d. None of these

Last Answer : b. Hard disk

Description : which of the 2 files are created by the assembler. a. _ List and object file b. Link and object file c. Botha &b d. None of these

Last Answer : a. _ List and object file

Description : Ingiven lines of code MOV AX,BL have different type of operands according to assembler for 8086 architecture these identifiers must be of. a. Different type only in byte b. Same type either in word or byte c. Botha &b d. None of these

Last Answer : b. Same type either in word or byte

Description : IBM-360 type language is example which supporting _—___—sJanguage. a. Micro b. Macro c. Botha &b d. None of these

Last Answer : b. Macro

Description : Full form of MIPS assembler is: a. Microprocessor without interlocked pipeline stage b. Microprocessor with interlocked pipeline stage c. Botha &b d. None of these

Last Answer : a. Microprocessor without interlocked pipeline stage

Description : Ina complex program, the overlaps: a. Branching b. Condition c. Botha &b d. None of these

Last Answer : a. Branching

Description : Avoid crossing flow lines. a. Flowchart b. Algorithm c. Botha &b d. None of these

Last Answer : a. Flowchart

Description : is useful to prepare detailed program documentation: a. Flowchart b. Algorithm c. Botha &b d. None of these

Last Answer : a. Flowchart

Description : Cache memory is located between main memory and : a. CPU b. Memory c. Botha &b d. None of these

Last Answer : a. CPU

Description : subroutine declaration come after procedure announcement: a. Global b. Local c. Botha &b d. None of these

Last Answer : a. Global

Description : Callis_ subroutine call. a. Conditional b. Unconditi c. Botha &b d. None of these

Last Answer : b. Unconditi

Description : The processed data is sent for output to standard __ device which by default is computer screen: a. Input b. Output c. Botha &b d. None of these

Last Answer : b. Output

Description : which of the following is interrupt mode. a. Task mode b. Executive mode c. Botha &b d. None of these

Last Answer : b. Executive mode

Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read

Last Answer : d. Address register and read

Description : Opcode is the machine instruction obtained from decoding instruction stored in. a. Stack pointer b. Address pointer Cc. Instruction register d. Incrementer

Last Answer : Cc. Instruction register

Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU

Last Answer : b. Main memory

Description : Who change the address in the program counter and cause the flow of control to be altered: a Shift manipulation b. Circular manipulation c. Program control instruction d. __ Allof these

Last Answer : c. Program control instruction

Description : Which register holds the next instruction to be executed:

Last Answer : c. Program control register

Description : Outputs of instruction/data path in CU are. a. Reg R/W b. Load/Reg-Reg c. ALU function select d. Load control e. Read control f. IR Latch g. JUMP/Branch/Next PC h_ = All of these

Last Answer : h_ = All of these

Description : On what method search in cache memory used by the system. a. Cache directing b. Cache mapping c. Cache controlling d. Cache invalidation

Last Answer : b. Cache mapping

Description : Each instruction is also accompanied by a___ : a. Microprocessor b. Microcode c. Both d. None of these

Last Answer : b. Microcode