sample and hold circuit by using op-amp
The n-channel MOSFET is driven by a control voltage VC acts as a switch. The control voltage VC is applied to the gate of the MOSFET. The circuit diagram can be split into three stages. First stage is the voltage follower second one is the switch and capacitor and the third one is a gain the voltage follower. When VC is high the MOSFET turns on and acts like a closed switch .This is sampling mode .The capacitor charges through the MOSFET to the instantaneous input voltage. As soon as VC=0 the MOSFET turns off and the capacitor is disconnected from OPMP1 output. Capacitor cannot discharge through amplifier A2 due to its high impedance. Thus this is the hold mode in which the capacitor holds the latest sample value. The time period during which the voltage across capacitor is equal to input voltage is called sample period. The time period during which the voltage across capacitor is constant is called Hold period.