Working: -
* When small a.c. signal is applied to the gate, it produces variation in the gate to source voltage. This produces variation in the drain current. As the gate to source voltage increases, the drain current also increases. As the result of this voltage drop across RD also increases. This causes the drain voltage to decreases.
* As the input voltage rises, gate to source voltage becomes less negative, it will increase the channel width and increase the level of drain current ID.
* As the input voltage falls, it will decrease the channel width and decrease the level of drain current ID. * Thus ID varies sinusoidally above its Q point value.
* The drain to source voltage VDS is given by
* VDS = VDD – IDRD
* Therefore as ID increases the voltage drop IDRD will also increase and voltage VDS will decrease.
* If ΔID is large for a small value of ΔVGS; the ΔVDS will also be large and we get amplification. Thus the AC output voltage VDS is 180º out of phase with AC input voltage.