A special type of timer is a watchdog timer, which will reset the system after a predefined timeout. Watchdog timer reset timer every X time unit, else timer generates a signal indicating that the system failed. A common use of watchdog timer is to enable an embedded system to restart itself in case of a failure.
Another common use is to support timeouts in a program while keeping the program structure simple.
Example of ATM timeout using a watchdog timer:-
In this example, a watchdog timer is used to implement a timer out for an automatic teller machine (ATM).
A normal ATM session introduces a user inserting a bank card, typing in a personal identification number (PIN), and then answering questions about whether to deposit or withdraw money, which account will be involved how much money will be involved, whether another transaction is desired and so on.
We want to design the ATM such that it will terminate the session if at any time the user does not press any button for a minute. In this case, the ATM will eject the bank card and terminate the session.
As oscillator signal, OSC is connected to prescaler that divides the oscillator frequency by 12 (OSC/12) to generate a signal clk.
The signal clock is connected to an 11-bit up counter scalereg. When scalereg overflows, it rolls over to "o", and its overflow output causes the 16-bit up counter timer reg to increment.
If timing overflows, it triggers the system reset or an interrupt. To reset the watchdog timer, checkreg must be enabled. Then a value can be loaded into timereg.
When a value is loaded into timereg, the checkreg register is automatically reset. If the checkreg register is not enabled. a value can not be loaded into timereg. This is to prevent erroneous software from unintentionally resetting the watchdog timer.