Application Specific Instruction Set Processor (ASIP)
Last Answer : An application specific instruction set processor (ASIP) can serve as a compromise between the general purpose processor and single-purpose processors. An ASIP is a Programmable processor ... fetch sequential data memory locations in parallel with other operations to further speed execution.
Show More
422 views
2 answers
asked
Jan 17, 2018
by
anonymous

A compiler is a translating program which A) Translates instruction of a high level language into machine language B) Translates entire source program into machine language program C) It is not involved in program’s execution D) All of above
Last Answer : Answer : D
Show More
1 view
1 answer

What do you call a program in execution? a) Command b) Process c) Task d) Instruction
Last Answer : Answer: b Explanation: Option Process is correct. A program is a set of instructions. A program in execution is called a process
Show More
3 views
1 answer
.jpg)
Which is the method by which instructions are selected for execution: a. Instruction selection b. — Selection control c. Instraction sequencing d. All of these
Last Answer : c. Instraction sequencing
Show More
7 views
1 answer

The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these
Last Answer : a. The address of next instruction to be run
Show More
5 views
1 answer

The time required to complete one instruction is called. a. Fetch time b. Execution time c. Control time d. All of these
Last Answer : b. Execution time
Show More
3 views
1 answer

Execution of instruction specified by instruction to perform: a. Operation b. Operands c. Both a &b d. None of these
Last Answer : a. Operation
Show More
4 views
1 answer

Which unit is necessary for the execution of instruction: a. Timing b. Control ce. Both d. None of these
Last Answer : ce. Both
Show More
3 views
1 answer

When subroutine is called contents of program counter is location address of __ instruction following call instruction is stored on _ __and program execution is transferred to __ address. a. Non ... , Stack and Main program Cc. Executable, Queue and Subroutine d. Executable, Stack and Subroutine
Last Answer : d. Executable, Stack and Subroutine
Show More
8 views
1 answer

Which of the following 2 task are performed to execute an instruction by MCU: a. Microinstruction execution b. Microinstruction sequencing c. Botha&b d. None of these
Last Answer : c. Botha&b
Show More
1 view
1 answer

Which microinstruction provide next instruction from control memory: a. Microinstruction execution b. Microinstruction Buffer c. Microinstruction decoder d. Microinstraction Sequencing
Last Answer : d. Microinstraction Sequencing
Show More
2 views
1 answer

Copy of instruction in cache memory is known as: a Execution cache b. Data cache c. Instruction cache d. Allof these
Last Answer : c. Instruction cache
Show More
2 views
1 answer

state keeps track of position related to execution of an instruction: a. Major b. Minor c. Botha & b d. None of these
Last Answer : a. Major
Show More
1 view
1 answer

A compiler is a translating program which a. Translates instruction of a high level language into machine language b. Translates entire source program into machine language program c. It is not involved in program’s execution d. All of above
Last Answer : All of above
Show More
8 views
1 answer

Find out the incorrect feature of Assembly language among following: a) It is also provided by the manufacturer b) One instruction for each computer operation c) Instruction codes are represented by mnemonics ... be assembled into machine language for execution d) All of the Above e) None of These
Last Answer : e) None of These
Show More
5 views
1 answer

The register which keeps track of the execution of a program and which contains the memory address of the instruction currently being executed is known as: a) Index Register b) Memory Address Register c) Program Counter d) None of The Above
Last Answer : c) Program Counter
Show More
4 views
1 answer

The simultaneous execution of two or more instructions is called- 1) Sequential Access 2) Reduced Instruction set computing 3) Multiprocessing 4) None of these
Last Answer : 3) Multiprocessing
Show More
2 views
1 answer

Pipelining strategy is called implement a. instruction execution b. instruction prefetch c. instruction decoding d. instruction manipulation
Last Answer : b. instruction prefetch
Show More
202 views
1 answer
asked
Aug 14, 2021
by
anonymous

A compiler is a translating program which a. Translates instruction of a high level language into machine language b. Translates entire source program into machine language program c. It is not involved in program’s execution d. All of above
Last Answer : d. All of above
Show More
27 views
1 answer
asked
Aug 14, 2021
by
anonymous

What are the five steps in MIPS instruction execution?
Last Answer : 1. Fetch instruction from memory. 2. Read registers while decoding the instruction. The regular format of MIPS instructions allows reading and decoding to occur simultaneously. 3. Execute the operation or calculate an address. 4. Access an operand in data memory. 5. Write the result into a register.
Show More
23 views
1 answer
asked
Aug 13, 2021
by
anonymous
.jpg)
AVR microcontroller executes most of the instruction in _________________. A. Single execution cycle. B. Double execution cycle. C. Both A& B D. None of the above.
Last Answer : architecture of embedded system consists of
Show More
43 views
2 answers
asked
Apr 4, 2021
by
anonymous

The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use memory bus. A memory read/write employs one machine cycle. For ... (A) 500 Kbytes/sec (B) 2.2 Mbytes/sec (C) 125 Kbytes/sec (D) 250 Kbytes/sec
Last Answer : (D) 250 Kbytes/sec
Show More
70 views
1 answer
asked
Feb 8, 2021
by
anonymous

A CPU handles interrupt by executing interrupt service subroutine................. (A) by checking interrupt register after execution of each instruction (B) by checking interrupt register ... cycle (C) whenever an interrupt is registered (D) by checking interrupt register at regular time interval
Last Answer : (A) by checking interrupt register after execution of each instruction
Show More
33 views
1 answer
asked
Feb 7, 2021
by
anonymous

If initial content of accumulator is 44 H, find out the new content of accumulator after execution of the instruction RR A
Last Answer : Contents of Acc will be 22H ( as RR A divides acc by 2)
Show More
123 views
1 answer
asked
May 21, 2020
by
anonymous

In an 8085 microprocessor, after the execution of XRA A instruction A) the carry flag is set B) the accumulator contains FFH C) the zero flag is set D) the accumulator contents are shifted left by one bit
Last Answer : In an 8085 microprocessor, after the execution of XRA A instruction the zero flag is set
Show More
2.9k views
1 answer
asked
Jun 4, 2018
by
anonymous

Which flag does not change by the execution of the instruction DCR B in 8085 microprocessor ? (a) Parity (b) Carry (c) Zero (d) Sign
Last Answer : Which flag does not change by the execution of the instruction DCR B in 8085 microprocessor ? (a) Parity (b) Carry (c) Zero (d) Sign
Show More
325 views
1 answer
asked
May 15, 2018
by
anonymous

A ______ Instruction at the end of interrupt service program takes the execution back to the interrupted program. (a) Forward (b) Return (c) Data (d) Line
Last Answer : A Return Instruction at the end of interrupt service program takes the execution back to the interrupted program.
Show More
346 views
1 answer
asked
May 13, 2018
by
anonymous

The Complement Accumulator (CMA) instruction of 8085 processor on execution affects a. Zero Flag b. Sign Flag c. Carry Flag d. None of the flags
Last Answer : B
Show More
1.1k views
1 answer
asked
Apr 12, 2018
by
anonymous

Normally, the FPGA resources are used less than 70% because: a. Routing becomes excessively complicated b. Power issues c. Clock frequency d. Simulation time increases
Last Answer : Normally, the FPGA resources are used less than 70% because: Routing becomes excessively complicated
Show More
320 views
1 answer
asked
May 17, 2018
by
anonymous

83 views
0 answers
asked
Apr 1, 2018
by
anonymous

77 views
0 answers
asked
Apr 1, 2018
by
anonymous

List and describe three general approaches to improve designer productivity.
Last Answer : Automation: The task of using a computer program to replace manual design effort. The program replaces manual design effort. Synthesis. Reuse: The ... correctness/completeness of each design step. Hardware/software co-simulation.
Show More
109 views
1 answer
asked
Mar 29, 2018
by
anonymous

Explain placement, routing, and sizing.
Last Answer : Placement: The task of placing and orienting every transistor somewhere on IC. Routing: The task of running wires between the transistors without inserting other wires or transistors. ... wires and transistor provide better performance but consume more power and require more silicon area.
Show More
78 views
1 answer
asked
Mar 28, 2018
by
anonymous

A single FSM can be converted to two smaller FSM. Justify.
Show More
591 views
0 answers
asked
Mar 28, 2018
by
anonymous

Last Answer : Common computation models: Sequential program model Statements, rules for composing statements, semantics for executing them Communicating process model ... Object-oriented model For breaking complex software into simpler, well-defined pieces
Show More
107 views
1 answer
asked
Mar 28, 2018
by
anonymous

Sketch internal design of 4x3 ROM.
Last Answer : The internal design of 4x3 ROM
Show More
778 views
1 answer
asked
Mar 28, 2018
by
anonymous

Explain the advantages and disadvantages of using memory I/O and standard I/O.
Last Answer : Memory mapped I/O and standard I/O are the two methods for communicating microprocessor with peripherals. Processor talks to both memory and peripheral using the same bus.Two ways to talk to a peripheral. ... of standard I/O is no loss of memory addresses to the use as I/O addresses.
Show More
171 views
1 answer
asked
Mar 26, 2018
by
anonymous

Explain parallel and wireless protocols.
Last Answer : Parallel protocols: PCI bus (Peripheral Components Interconnect): PCI stands for Peripheral Components Interconnect. PCI bus is used as a communication line to transmit signals and data ... provide the basis for wireless network products using the Wi-Fi brand.
Show More
100 views
1 answer
asked
Mar 26, 2018
by
anonymous

Explain memory hierarchy.
Last Answer : Memory hierarchy: Main memory is large, inexpensive, slow memory stores entire program and data. Cache memory is small, expensive, fast memory stores copy of likely accessed parts of large ... In memory hierarchy the smaller memory is faster and larger memory storage is slower.
Show More
186 views
1 answer
asked
Mar 26, 2018
by
anonymous

Explain memory write ability and storage permanence with suitable diagram.
Last Answer : Write ability and storage permanence of memories: Write ability is the manner and speed at which memory can be written. Storage permanence is the ability of memory to hold stored bits ... Holds bits after power is no longer supplied. High end and middle range of storage permanence.
Show More
3.5k views
1 answer
asked
Mar 24, 2018
by
anonymous

Describe different RT level computational and sequential components used to design single function processors.
Last Answer : RT-level combinational components:- To reduce the complexity in digital logic, combinational components are used, which are more powerful than logic gates. Such combinational ... during a clock edge. An asynchronous inputs value effects the circuit independent of the clock.
Show More
244 views
1 answer
asked
Mar 21, 2018
by
anonymous

Build using minimum number of CMOS gates. Three input NAND gate. Two input NOR gate Three input NOR gate Two input AND gate Two input OR gate
Last Answer : Three input NAND gate. Two input NOR gate Three input NOR gate Two input AND gate Two input OR gate
Show More
213 views
1 answer
asked
Mar 21, 2018
by
anonymous

Explain the various steps involved in designing a custom single-purpose processor.
Last Answer : A single purpose processor is a digital circuit designed to execute exactly one program. It is also known as co-processor, accelerator or peripheral. It contains only ... for small quantities. Performance may not match general-purpose processors for same applications.
Show More
412 views
1 answer
asked
Mar 21, 2018
by
anonymous

If Moor's law continues to hold, predict the approximation number of transistor per leading edge IC in the year. 1.2030 2.2050
Last Answer : If Moor's law continues to hold, predict the approximation number of transistor per leading edge IC in the year.1.20302.2050
Show More
60 views
1 answer
asked
Mar 21, 2018
by
anonymous

Compare the annual growth rate of 1.IC capacity 2.Designer productivity.
Last Answer : Compare the annual growth rate of 1.IC capacity2.Designer productivity.
Show More
99 views
1 answer
asked
Mar 21, 2018
by
anonymous

Explain Inter-process Communication (IPC) using mailbox/queue.
Last Answer : Inter-process communication using mailbox: Mailbox is the Interprocess communication mechanism. A process puts a data message for another process in the mailbox. Mailbox is also called as message exchange. ... a message. In mailbox IPC the sender need not to know the name of the receiver.
Show More
140 views
1 answer
asked
Mar 18, 2018
by
anonymous

Explain arbitration. What is priority arbitrator?
Last Answer : Arbitration: IF multiple peripherals are connected to microprocessor or DMA controller or any resource and they request services simultaneously so which peripheral will get serviced first this is ... Peripherals make requests to arbiter and arbiter makes requests to the resource.
Show More
101 views
1 answer
asked
Mar 17, 2018
by
anonymous

Explain FSM and concurrent process with example.
Last Answer : Finite State Machine (FSM): Finite state machine is a machine which have a transition from state to state. The system have some number of states and at a time the system can ... Y seconds. In sequential execution, the processor executes single task which causes poor processor utilization.
Show More
126 views
1 answer
asked
Mar 17, 2018
by
anonymous

Compose 1k x 8 ROMS into 8k x 8 ROM.
Last Answer : 1k x 8 ROMS into 8k x 8 ROM:
Show More
1.7k views
1 answer
asked
Mar 15, 2018
by
anonymous

What is design technology? Explain top down design process.
Last Answer : Design technology: Design technology is the manner in which we convert our concept desired system into an implementation. The three main design technologies are 1. Compilation/Synthesis ... general purpose processors and A Gate-level Netlist for special-purpose processors.
Show More
168 views
1 answer
asked
Mar 14, 2018
by
anonymous
