**Description :** How many minimum number of NOR gates are required to realize a two-input X-OR gate?

**Last Answer :** 5

**Description :** In standard TTL gates, the totem pole output stage is primarily used to (A) increase the noise margin of the gate (B) decrease the output switching delay (C) facilitate a wired OR logic connection (D) increase the output impedance of the circuit

**Last Answer :** In standard TTL gates, the totem pole output stage is primarily used to decrease the output switching delay

**Description :** The complete set of only those Logic Gates designated as Universal Gates is (A) NOT, OR and AND Gates (B) XNOR, NOR and NAND Gates (C) NOR and NAND Gates (D) XOR, NOR and NAND Gates

**Last Answer :** The complete set of only those Logic Gates designated as Universal Gates is NOR and NAND Gates

**Description :** IC which has quad 2 input AND gates (A) 7411 (B) 7404 (C)7400 (D) 7408

**Last Answer :** IC which has quad 2 input AND gates 7408

**Description :** Which of the following gates can be used to realize all possible combinational logic functions? (i) OR gate (ii) NOR gate (iii) Exclusive OR gate (iv) NAND gate (v) AND gate (A) (iii), (iv) and (v) (B) (i), (iii) and (iv) (C) (ii) and (iv) (D) (i) and (v)

**Last Answer :** Which of the following gates can be used to realize all possible combinational logic functions? (i) OR gate (ii) NOR gate (iii) Exclusive OR gate (iv) NAND gate (v) AND gate (A) (iii), (iv) and (v) (B) (i), (iii) and (iv) (C) (ii) and (iv) (D) (i) and (v)

**Last Answer :** NAND gates are preferred over others because these can be used to make any gate.

**Last Answer :** In integrated circuit electronics the basic universal gate is AND gate.

**Description :** How Many Basic Logic Gates ?

**Last Answer :** Basic Logic Gate three. OR, AND, NOT

**Description :** How many basic gates and what are they ?

**Last Answer :** There are three basic gates , namely- ( a) AND (b) OR (c) NOT

**Description :** What are the basic gates ?

**Last Answer :** Basic gates AND, OR and NOT .

**Description :** What are the basic logic gates ?

**Last Answer :** Basic Reasoning Gates. Namely: Or Gate , End Gate and Non Gate.

**Description :** Which of the listed logic gates is considered to be a BASIC building block (basic logic gate) used in logic diagrams? A. NAND B. OR C. NOR D. All of the above.

**Last Answer :** Answer: B

**Description :** What are the basic digital logic gates?

**Last Answer :** The three basic logic gates are • AND gate • OR gate • NOT gate

**Description :** A basic S -R flip-flop can be constructed by cross -coupling which basic logic gates : - a) AND or OR gates b) XOR or XNOR gates c) NOR or NAND gates d) AND or NOR gates

**Last Answer :** A basic S -R flip-flop can be constructed by cross -coupling which basic logic gates : - NOR or NAND gates

**Description :** List out features of any four addressing modes of 8051.

**Last Answer :** 1.Immediate addressing mode: In this Immediate Addressing Mode, the data is provided in the instruction itself. The data is provided immediately after the opcode. These are some examples of Immediate Addressing Mode. MOVA ... us see some examples of this mode. MOV 0E5H, @R0 MOV @R1, 80H

**Description :** List out any four assembler directives and state their functions.

**Last Answer :** ORG directive: It is used to specify starting address of the Program. A 16bit address follows ORG ORG 0020H will start program from 0020H memory location. END directive: It indicates end of the ... that when the label appears in the program, itp constant value will be substituted for the label.

**Description :** State functions of preset, clear, clock and SR inputs related to SR flip flop.

**Last Answer :** Preset Input: is an asynchronous input to set the Q output to 1 Clear Input: is also asynchronous input to reset the Q output to 0 Clock Input: is used to input external logic clock pulse (HIGH-LO) to ... set the Q output. And R is the reset input which is used to reset Q output of the flipflop.

**Description :** State Demorgan's theorem's and prove both theorems using truth table.

**Last Answer :** De Morgan's 1st theorem states that when the OR sum of two variables is inverted, this is the same as inverting each variable individually and then ANDing these inverted variables. De Morgan's 2nd ... individually and then ORing them. In Boolean equation form it can be written as

**Description :** Define following terms related to logic families : (i) Noise Margin (ii) FAN-OUT (iii) Propagation delay (iv) Power dissipation

**Last Answer :** i) Noise immunity is measured in terms of noise margin. High state Noise margin = VNH = VOH(min) - VIH(min) Low state Noise margin = VNL = VIL(max) - VOL(max) i) The fan-out is defined as the ... logical 0 state (HIGH to LOW) iii) Average power dissipation is defined as PD(avg) = ICC(avg) * VCC

**Description :** Find out number of data lines required to interface 16 LEDs arrange in the 4 x 4 matrix form.

**Last Answer :** 4+4=8, eight lines are required for 4x4 matrix of 16 LEDs

**Description :** If initial content of accumulator is 44 H, find out the new content of accumulator after execution of the instruction RR A

**Last Answer :** Contents of Acc will be 22H ( as RR A divides acc by 2)

**Description :** Identify direct addressing instructions from following instructions : (i) MOV RO, R5 (ii) MOV RO, 80 H (iii) MOV RO, #75H (iv) ADD A, 45 H

**Last Answer :** Instructions ii) and iv) are direct addressing as 80H and 45H are direct addresses

**Description :** Define the term 'Multiplexer'. State two examples of multiplexer.

**Last Answer :** A digital multiplexer or data selector is a logic circuit that accepts several (many) digital data inputs and selects one of them at any given time to pass on to the output. 1. Two input multiplexer 2. Four input multiplexer 3. Eight input multiplexer

**Description :** The output of a JK flip-flop with asynchronous preset and clear inputs is ‘1’. The output can be changed to ‘0’ with one of the following conditions by applying A) J = 0, K = 0 and using a clock B) J = 1, K = 0 and using the clock C) Asynchronous preset input D) J = 1, K = 1 and using the clock

**Last Answer :** The output of a JK flip-flop with asynchronous preset and clear inputs is ‘1’. The output can be changed to ‘0’ with one of the following conditions by applying J = 1, K = 1 and using the clock

**Description :** Which one of the following logic circuit has the highest speed as compared to the currently available logic circuits? A) Resistance-transistor logic B) Emitter-coupled logic C) Integrated-injection logic D) Diode-transistor logic

**Last Answer :** Which one of the following logic circuit has the highest speed as compared to the currently available logic circuits? A) Resistance-transistor logic B) Emitter-coupled logic C) Integrated-injection logic D) Diode-transistor logic

**Description :** What is the 2's complement of 01101? A) 10010 B) 10011 C) 1100 D) 1001

**Last Answer :** What is the 2's complement of 01101? A) 10010 B) 10011 C) 1100 D) 1001

**Description :** The current mode logic (CML) is same as A) LSI B) CMOS C) TTL D) ECL

**Last Answer :** The current mode logic (CML) is same as ECL

**Description :** Which code is used in constructing k-maps? A) Hamming code B) 2 out of 5 code C) BCD code D) Gray code

**Last Answer :** Which code is used in constructing k-maps? A) Hamming code B) 2 out of 5 code C) BCD code D) Gray code

**Description :** For a NAND gate, when one or more inputs are low then the output will be A) Low B) High C) Alternately high and low D) High or low depending on relative magnitude of inputs

**Last Answer :** For a NAND gate, when one or more inputs are low then the output will be High

**Description :** Decimal equivalent of Hexadecimal number (C3B1)16 is: A) 12197 B) 32097 C) 52097 D) 50097

**Last Answer :** Decimal equivalent of Hexadecimal number (C3B1)16 is: 50097

**Description :** A NOR gate is equivalent to a bubbled AND gate. This statement is an outcome of: (1) De Morgan’s Law (2) Involution Law (3) Law of Absorption (4) Idempotent Law

**Last Answer :** A NOR gate is equivalent to a bubbled AND gate. This statement is an outcome of: De Morgan’s Law

**Description :** Initially the number decimal 8 is stored. If instruction RAL is executed twice, the final number stored will be: (1) Decimals 8 (2) Decimal 16 (3) Decimal 32 (4) Decimal 2

**Last Answer :** Initially the number decimal 8 is stored. If instruction RAL is executed twice, the final number stored will be: Decimal 32

**Description :** Determine the output frequency for a frequency division circuit that contains 12 flip–flops with an input clock frequency of 20.48 MHz: (1) 10.24 kHz (2) 5 kHz (3) 30.24 kHz (4) 15 kHz

**Last Answer :** Determine the output frequency for a frequency division circuit that contains 12 flip–flops with an input clock frequency of 20.48 MHz: 5 kHz

**Description :** The output of an exclusive–NOR gate is 1. Which input combination is correct? (1) A = 1, B = 0 (2) A = 0, B = 1 (3) A = 0, B = 0 (4) None of these

**Last Answer :** The output of an exclusive–NOR gate is 1. Which input combination is correct? (1) A = 1, B = 0 (2) A = 0, B = 1 (3) A = 0, B = 0 (4) None of these

**Description :** How many flip-flops are required to build a binary counter circuit to count from 0 to 1023 ? (a) 1 (b) 6 (c) 10 (d) 23

**Last Answer :** (c)10

**Description :** In a positive edge triggered JK flip-flop, J = 1, K = 0 and clock pulse is rising, Q will be (a) 0 (b) 1 (c) showing no change (d) toggle

**Last Answer :** In a positive edge triggered JK flip-flop, J =1, K= 0 and clock pulse is rising, a Q will be 1

**Description :** Output of NAND gate is 0. for three inputs when:

**Last Answer :** Output of NAND gate is 0. for three inputs when: all the inputs are 1

**Description :** In a PLL, lock occurs when the (A) input frequency and the VCO frequency are the same (B) Phase error is 1800 (C) VCO frequency is double the input frequency (D) Phase error is 900

**Last Answer :** In a PLL, lock occurs when the input frequency and the VCO frequency are the same

**Description :** The following logic families have their propagation delay. Arrange them from lowest propagation delay to highest propagation delay. 1. TTL (Standard) 2. ECL 3. Low power CMOS 4. DTL (A) 2, 1, 4 and 3 (B) 2, 4, 1 and 3 (C) 4, 2, 3 and 1 (D) 1, 2, 3 and 4

**Last Answer :** The following logic families have their propagation delay. Arrange them from lowest propagation delay to highest propagation delay. 1. TTL (Standard) 2. ECL 3. Low power CMOS 4. DTL (A) 2, 1, 4 and 3 (B) 2, 4, 1 and 3 (C) 4, 2, 3 and 1 (D) 1, 2, 3 and 4

**Description :** In successive approximation converter input to the comparator is through (A) DAC (B) Latch (C) Flip-flop (D) Sample and hold circuit

**Last Answer :** In successive approximation converter input to the comparator is through DAC

**Description :** Read the following statements: i. Gate is a combinational logic. ii. JK Flip-flop in toggle mode is not combinational logic. iii. MSJK Flip-flop suffers from race-around. iv. Counters are sequential circuits. Which choice is correct? (A) i, ii (B) i, ii, iv (C) ii, iii, iv (D) i, ii, iii

**Last Answer :** Read the following statements: i. Gate is a combinational logic. ii. JK Flip-flop in toggle mode is not combinational logic. iii. MSJK Flip-flop suffers from race-around. iv. Counters are sequential circuits. Which choice is ... (A) i, ii (B) i, ii, iv (C) ii, iii, iv (D) i, ii, iii

**Description :** Which of the following peripherals provide I/O facilities? i. 8279 ii. 8155 iii. 8259 iv. 8255 (A) i, ii (B) ii, iii (C) iii, iv (D) ii, iv

**Last Answer :** Which of the following peripherals provide I/O facilities? i. 8279 ii. 8155 iii. 8259 iv. 8255 (A) i, ii (B) ii, iii (C) iii, iv (D) ii, iv

**Description :** Which of the following is error correcting code? (A) EBCDIC (B) GRAY (C) Hamming (D) ASCII

**Last Answer :** Which of the following is error correcting code? (A) EBCDIC (B) GRAY (C) Hamming (D) ASCII

**Description :** The number of switching functions of 3 variables is (A) 8 (B) 64 (C) 128 (D) 256

**Last Answer :** The number of switching functions of 3 variables is 8

**Description :** No. of flip-flops used in decade counter (a) 3 (b) 2 (c) 4 (d) None of these

**Last Answer :** 4

**Description :** A half adder can be constructed from

**Last Answer :** A half adder can be constructed from One XOR gate and one 'AND‘ gate with their input connected in parallel

**Description :** The decimal equivalent of a Hexadecimal no. (F8E6)16 is

**Last Answer :** The decimal equivalent of a Hexadecimal no. (F8E6)16 is (63,718)10

**Description :** Hexadecimal equivalent of the decimal number 25610 is

**Last Answer :** Hexadecimal equivalent of the decimal number 25610 is 10016

**Description :** The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in figure is 10 KHZ. The frequency of the signal at Q is A) 10 KHz B) 2.5 KHz C) 20 KHz D) 5 KHz

**Last Answer :** The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in figure is 10 KHZ. The frequency of the signal at Q is 5 KHz

**Description :** For the circuit shown in figure, the Boolean expression for the output y in terms of inputs P, Q, R and S is

**Last Answer :** For the circuit shown in figure, the Boolean expression for the output y in terms of inputs P, Q, R and S is P+Q+R+S