Design technology:
Design technology is the manner in which we convert our concept desired system into an implementation.
The three main design technologies are
1. Compilation/Synthesis
2. Libraries/IP
3. Test/Verification
1.Compilation/Synthesis:-
This design technology allows a designer to define functionality in an abstract manner and the technology will automatically generate the lower level implementation details. Designer benefit because they do not have to be aware of the lower level implementation details, which will increase their productivity.
2.Libraries/IP:-
Libraries and IP are essentially catalogs of pre-existing implementations. This benefits the designer because they don't have to be "re-invent the wheel".
3.Test/Verification:-
This design technology ensures that the functionality of a system is correct. This saves the designer time by preventing debugging at the low level.
Top-down design process:
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The designer refines the system through several abstraction levels.
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At the system level, the designer describes the desired functionality in some language, often a natural language like English, but preferably an executable language like 'C' & this is called system specifications.
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The designer refines this specification by distributing a portion of it among several general or single-purpose processors, yielding behavior specification for each processor.
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The designer refines these specifications into register transfer (RT) specifications by converting behavior on general purpose processors to assembly code, and by converting behavior on single-purpose processors to a connection of register-transfer components and state machine.
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The designer then refines the register transfer level specifications of a single purpose processor into a logic specifications consisting of boolean equations.
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No refinement of a general-purpose processors assembly code is done at this level.
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Finally, the designer refines the remaining specifications into an implementation, consisting of
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Machine codes for general purpose processors and
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A Gate-level Netlist for special-purpose processors.