Circuit diagram of amplitude limiter:-
Explanation:- 1. In frequency modulation, the signal amplitude is held constant while the carrier frequency is varied. 2. Any noise that contaminates the signal will manifest itself as a change in amplitude. 3. The first limiter is a pair of back-to-back diodes D1 and D2. 4. Diode D1 will conduct when the input signal is grater than 0.7V on the positive peak, and diode D2 will conduct on the portion of the negative half-cycle that exceeds -0.7VpK of the input signal. 5. The second form of limiting in the figure is the transistor amplifier itself, which has a gain of 10. 6. When the base signal reaches 1.4V p-p, the collector voltage becomes ten times larger. 7. The collector and emitter currents increase, raising the emitter voltage at the same time that the collector is going lower. 8. The total collector change is 9.4 V, limiting the output signal to 9.4 V p-p instead of the alternately driven into saturation and cutoff, it limits the signal amplitude