Description : Which of the following is the fastest logic? (A) ECL (B) TTL (C) CMOS (D) LSI
Last Answer : (A) ECL
Description : The digital logic family which has the lowest propagation delay time is (A) ECL (B) TTL (C) CMOS (D) PMOS
Last Answer : Ans: A The digital logic family which has the lowest propagation delay time is ECL (Lowest propagation delay time is possible in ECL because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated).
Description : Which of the following is the fastest logic (A) TTL (B) ECL (C) CMOS (D) LSI
Last Answer : Ans: B ECL is the fastest logic family of all logic families. (High speeds are possible in ECL because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated.
Description : The digital logic family which has minimum power dissipation is (A) TTL (B) RTL (C) DTL (D) CMOS
Last Answer : (D) CMOS The digital logic family which has minimum power dissipation is CMOS. (CMOS being an unipolar logic family, occupy a very small fraction of silicon Chip area)
Description : Which of following consume minimum power (A) TTL. (B) CMOS. (C) DTL. (D) RTL.
Last Answer : Ans: B CMOS consumes minimum power as in CMOS one p-MOS & one n-MOS transistors are connected in complimentary mode, such that one device is ON & one is OFF.
Description : The MSI chip 7474 is (A) Dual edge triggered JK flip-flop (TTL). (B) Dual edge triggered D flip-flop (CMOS). (C) Dual edge triggered D flip-flop (TTL). (D) Dual edge triggered JK flip-flop (CMOS).
Last Answer : Ans: C MSI chip 7474 dual edge triggered D Flip-Flop.
Description : CMOS circuits are extensively used for ON-chip computers mainly because of their extremely (A) low power dissipation. (B) high noise immunity. (C) large packing density. (D) low cost.
Last Answer : Ans: C Because CMOS circuits have large packing density.
Description : CMOS circuits consume power (A) Equal to TTL (B) Less than TTL (C) Twice of TTL (D) Thrice of TTL
Last Answer : Ans: B As in CMOS one device is ON & one is Always OFF so power consumption is low.
Description : In a positive logic system, logic state 1 corresponds to (A) positive voltage (B) higher voltage level (C) zero voltage level (D) lower voltage level
Last Answer : (B) higher voltage level We decide two voltages levels for positive digital logic. Higher voltage represents logic 1 & a lower voltage represents logic 0.
Description : The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either (A) a NAND or an EX-OR (B) an OR or an EX-NOR (C) an AND or an EX-OR (D) a NOR or an EX-NOR
Last Answer : (D) a NOR or an EX-NOR
Description : An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the input signal which can be used for proper operation of the counter is approximately (A) 1 MHz. (B) 500 MHz. (C) 2 MHz. (D) 4 MHz.
Last Answer : Maximum time taken for all flip-flops to stabilize is 75ns x 8 + 50 = 650ns. Frequency of operation must be less than 1/650ns = 1.5 MHz.
Description : Define combinational logic
Last Answer : When logic gates are connected together to produce a specified output for certain specified combinations of input variables, with no storage involved, the resulting circuit is called combinational logic.
Description : A full adder logic circuit will have (A) Two inputs and one output. (B) Three inputs and three outputs. (C) Two inputs and two outputs. (D) Three inputs and two outputs.
Last Answer : Ans: D A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there.
Description : Karnaugh map is used for the purpose of (A) Reducing the electronic circuits used. (B) To map the given Boolean logic function. (C) To minimize the terms in a Boolean expression. (D) To maximize the terms of a given a Boolean expression.
Last Answer : (C) To minimize the terms in a Boolean expression.
Description : A universal logic gate is one, which can be used to generate any logic function. Which of the following is a universal logic gate? (A) OR (B) AND (C) XOR (D) NAND
Last Answer : Ans: D NAND can generate any logic function.
Description : Which TTL logic gate is used for wired ANDing (A) Open collector output (B) Totem Pole (C) Tri state output (D) ECL gates
Last Answer : Ans: A Open collector output.
Description : The information in ROM is stored (A) By the user any number of times. (B) By the manufacturer during fabrication of the device. (C) By the user using ultraviolet light. (D) By the user once and only once.
Last Answer : (B) By the manufacturer during fabrication of the device.
Description : A device which converts BCD to Seven Segment is called (A) Encoder (B) Decoder (C) Multiplexer (D) Demultiplexer
Last Answer : Ans: B A device which converts BCD to Seven Segment is called DECODER. (A decoder coverts binary words into alphanumeric characters.)
Description : The device which changes from serial data to parallel data is (A) COUNTER (B) MULTIPLEXER (C) DEMULTIPLEXER (D) FLIP-FLOP
Last Answer : Ans: C The device which changes from serial data to parallel data is demultiplexer. (A demultiplexer takes in data from one line and directs it to any of its N outputs depending on the status of the select inputs.)
Description : Design Y=AB.CD using CMOS logic.
Last Answer : Y=AB.CD using CMOS logic
Description : What is the decimal value of 2-1? 33) A) 0.1 B) 0.25 C) 0.5 D) 0.05
Last Answer : C) 0.5
Description : What is the decimal value of 2-2? 11) A) 0.5 B) 0.125 C) 0.2 D) 0.25
Last Answer : D) 0.25
Description : What is the decimal value of 20? 127) A) 2 B) 0 C) 1 D) 3
Last Answer : C) 1
Description : Convert the decimal number 0.0625 to binary. 100) A) 0000.0111 B) 0000.1110 C) 0000.0011 D) 0000.0001
Last Answer : D) 0000.0001
Description : What is the decimal value of 2-3? 74) A) 0.25 B) 0.75 C) 0.125 D) 0.8
Last Answer : C) 0.125
Description : Which binary value equals 2-1? 61) A) 1.0000 B) 0.0010 C) 0.0001 D) 0.1000
Last Answer : D) 0.1000
Description : What numeric symbols are used in the binary number system? 58) A) 0 through 8 B) 0, 1, 2 C) 1, 2 D) 0, 1
Last Answer : D) 0, 1
Description : What is the decimal value of 2 1? 35) A) 1 B) 4 C) 2 D) 0
Last Answer : C) 2
Last Answer : C) 8716
Description : Convert the binary number 0000.1010 to decimal. 6) A) 0.10 B) 0.55 C) 0.50 D) 0.625
Last Answer : D) 0.625
Description : For JK flipflop J = 0, K=1, the output after clock pulse will be (A) 1. (B) no change. (C) 0. (D) high impedance.
Last Answer : Ans: C J=0, K=1, these inputs will reset the flip-flop after the clock pulse. So whatever be the previous output, the next state will be 0.
Description : The output of a JK flipflop with asynchronous preset and clear inputs is 1'. The output can be changed to 0' with one of the following conditions. (A) By applying J = 0, K = 0 and using a clock. (B) ... (C) By applying J = 1, K = 1 and using the clock. (D) By applying a synchronous preset input.
Last Answer : Ans: C Preset state of JK Flip-Flop =1 With J=1 K=1 and the clock next state will be complement of the present state.
Description : The output of SR flip flop when S=1, R=0 is (A) 1 (B) 0 (C) No change (D) High impedance
Last Answer : Ans: A As for the SR flip-flop S=set input R=reset input ,when S=1, R=0, Flip-flop will be set.
Description : For JK flip flop with J=1, K=0, the output after clock pulse will be (A) 0. (B) 1. (C) high impedance. (D) no change.
Last Answer : (B) 1.
Description : When the set of input data to an even parity generator is 0111, the output will be (A) 1 (B) 0 (C) Unpredictable (D) Depends on the previous input
Last Answer : Ans: B In even parity generator if number of 1 is odd then output will be zero.
Description : Convert the decimal number 10.5 to binary. 92) A) 1100.1000 B) 1010.0101 C) 1010.1000 D) 1011.1000
Last Answer : C) 1010.1000
Description : Convert octal 54 to decimal. 5) A) 6410 B) 5810 C) 7610 D) 4410
Last Answer : D) 4410
Description : How many address bits are required to represent 4K memory (A) 5 bits. (B) 12 bits. (C) 8 bits. (D) 10 bits.
Last Answer : (B) 12 bits.
Description : How many select lines will a 32:1 multiplexer will have (A) 5. (B) 8. (C) 9. (D) 11.
Last Answer : (A) 5.
Description : The number of control lines for 32 to 1 multiplexer is (A) 4. (B) 5. (C) 16. (D) 6.
Last Answer : Ans: B The number of control lines for 32 (2^5) and to select one input among them total 5 select lines are required.
Description : The number of control lines for 16 to 1 multiplexer is (A) 2. (B) 4. (C) 3. (D) 5.
Last Answer : (B) 4.
Description : How many flip-flops are required to construct mod 30 counter (A) 5 (B) 6 (C) 4 (D) 8
Last Answer : (A) 5
Description : How many select lines will a 16 to 1 multiplexer will have (A) 4 (B) 3 (C) 5 (D) 1
Last Answer : (A) 4
Description : How many AND gates are required to realize Y = CD+EF+G (A) 4 (B) 5 (C) 3 (D) 2
Last Answer : 2
Description : If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is (A) 1000 Hz (B) 500 Hz (C) 333 Hz (D) 12.5 Hz.
Last Answer : (D) 12.5 Hz.
Description : A ring counter consisting of five Flip-Flops will have (A) 5 states (B) 10 states (C) 32 states (D) Infinite states.
Last Answer : Ans: A A ring counter consisting of Five Flip-Flops will have 5 states.
Description : How many Flip-Flops are required for mod–16 counter? (A) 5 (B) 6 (C) 3 (D) 4
Last Answer : (D) 4
Description : The number of control lines for a 8 – to – 1 multiplexer is (A) 2 (B) 3 (C) 4 (D) 5
Last Answer : Ans: B The number of control lines for an 8 to 1 Multiplexer is 3 (The control signals are used to steer any one of the 8 inputs to the output)
Description : Voltage can be stepped up from 6 to approximately a) 10,000 volts b) 15.00 0 volts c) 20,000 volts d) 25,000 volts
Last Answer : c) 20,000 volts
Description : Define Asynchronous sequential circuit?
Last Answer : In asynchronous sequential circuits change in input signals can affect memory element at any instant of time.