Recent questions tagged visi

Description : Explain the operation of NMOS Enhancement transistor.

Last Answer : Explanation (2) Diagram (2) Operation (4)

Description : Explain the silicon semiconductor fabrication process.

Last Answer : Silicon wafer Preparation (2) Epitaxial Growth (2) Oxidation (2) Photolithography (2) Diffusion(2) Ion Implantation (2) Isolation technique (2) Metallization (1) Assembly processing & Packaging (1)

Description : Explain the operation of PMOS Enhancement transistor

Last Answer : xplanation (2) Diagram (2) Operation (4)

Description : Explain the latch up prevention techniques.

Last Answer : Definition (2) Explanation (2) Diagram (2)

Description : explain with neat diagrams the various CMOS fabrication

Last Answer : technology P-well process (4) N-well process (4) Silicon-On-Insulator Process (4) Twin- tub Process (4)

Description : What is an antifuse?

Last Answer : An antifuse is normally high resistance (>100M ). On application of appropriate programming voltages, the antifuse is changed permanently to a low-resistance structure (200-500 ).

Description : What are the different methods of programming of PALs?

Last Answer : The programming of PALs is done in three main ways: Fusible links UV – erasable EPROM EEPROM (E2PROM) – Electrically Erasable Programmable ROM

Description : What are two components of Power dissipation.

Last Answer : There are two components that establish the amount of power dissipated in a CMOS circuit. These are: i) Static dissipation due to leakage current or other current drawn continuously from ... Dynamic dissipation due to - Switching transient current - Charging and discharging of load capacitances.

Description : Define Delay time

Last Answer : Delay time, d is the time difference between input transition (50%) and the 50% output level. This is the time taken for a logic transition to pass from input to output.

Description : Define Fall time

Last Answer : Fall time, f is the time taken for a waveform to fall from 90% to 10% of its steady-state value.

Description : Define Rise time

Last Answer : Rise time, r is the time taken for a waveform to rise from 10% to 90% of its steady-state value.

Description : What is Latch – up?

Last Answer : Latch up is a condition in which the parasitic components give rise to the establishment of low resistance conducting paths between VDD and VSS with disastrous results. Careful control during fabrication is necessary to avoid this problem.

Description : .What is Channel-length modulation?

Last Answer : The current between drain and source terminals is constant and independent of the applied voltage over the terminals. This is not entirely correct. The effective length of the conductive channel is ... depletion region at the drain junction to grow, reducing the length of the effective channel.

Description : What is Body effect?

Last Answer : The threshold volatge VT is not a constant w. r. to the voltage difference between the substrate and the source of MOS transistor. This effect is called substrate-bias effect or body effect.

Description : Define Threshold voltage in CMOS?

Last Answer : The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to source current, IDS effectively drops to zero.

Description : Compare between CMOS and bipolar technologies.

Last Answer : o CMOS Technology Bipolar technology o Low static power dissipation o High input impedance (low drive current) o Scalable threshold voltage o High noise margin o High packing density o High delay sensitivity to load (fanout limitations) o Low output drive current o Low gm (gm Vin)

Description : What are the different MOS layers?

Last Answer : _ n-diffusion _ p-diffusion _ Polysilicon _ Metal

Description : What are the different operating regions foe an MOS transistor?

Last Answer : _ Cutoff region _ Non- Saturated Region _ Saturated Region

Description : Why NMOS technology is preferred more than PMOS technology?

Last Answer : N- channel transistors has greater switching speed when compared tp PMOS

Description : What is pull up device?

Last Answer : A device connected so as to pull the output voltage to the upper supply voltage usually VDD is called pull up device.

Description : .What is pull down device?

Last Answer : A device connected so as to pull the output voltage to the lower supply voltage usually 0V is called pull down device.

Description : Define Short Channel devices?

Last Answer : Transistors with Channel length less than 3- 5 microns are termed as Short channel devices. With short channel devices the ratio between the lateral & vertical dimensions are reduced.

Description : .What is the fundamental goal in Device modeling?

Last Answer : To obtain the functional relationship among the terminal electrical variables of the device that is to be modeled.

Description : What are the advantages of CMOS process?

Last Answer : Low Input Impedance Low delay Sensitivity to load.

Description : What are the advantages of CMOS process?

Last Answer : Low power Dissipation High Packing density Bi directional capability

Description : What are the basic processing steps involved in BiCMOS process? Additional masks defining P base region

Last Answer : _ N Collector area _ Buried Sub collector (SCCD) _ Processing steps in CMOS process

Description : What is BiCMOS Technology?

Last Answer : It is the combination of Bipolar technology & CMOS technology.

Description : What are the advantages of Silicon-on-Insulator process?

Last Answer : _ No Latch-up _ Due to absence of bulks transistor structures are denser than bulk silicon.

Description : .What are the steps involved in twin-tub process?

Last Answer : Tub Formation _ Thin-oxide Construction _ Source & Drain Implantation _ Contact cut definition _ Metallization.

Description : Give the different types of CMOS process?

Last Answer : _ p-well process _ n-well process _ Silicon-On-Insulator Process _ Twin- tub Process

Description : When the channel is said to be pinched –off?

Last Answer : If a large Vds is applied this voltage with deplete the Inversion layer .This Voltage effectively pinches off the channel near the drain.

Description : What is Depletion mode Device?

Last Answer : The Device that conduct with zero gate bias.

Description : What is Enhancement mode transistor?

Last Answer : The device that is normally cut-off with zero gate bias.

Description : What are the different layers in MOS transistors?

Last Answer : Drain , Source & Gate

Description : What is the transistors CMOS technology provides?

Last Answer : n-type transistors & p-type transistors.

Description : .Different types of oxidation?

Last Answer : Dry & Wet Oxidation

Description : What are the various Silicon wafer Preparation? _

Last Answer : Crystal growth & doping _ Ingot trimming & grinding _ Ingot slicing _ Wafer polishing & etching _ Wafer cleaning.

Description : Give the basic process for IC fabrication

Last Answer : _ Silicon wafer Preparation _ Epitaxial Growth _ Oxidation _ Photolithography _ Diffusion _ Ion Implantation _ Isolation technique _ Metallization _ Assembly processing & Packaging

Description : .Give the variety of Integrated Circuits?

Last Answer : _ More Specialized Circuits _ Application Specific Integrated Circuits(ASICs) _ Systems-On-Chips

Description : Give the advantages of IC?

Last Answer : _ Size is less _ High Speed _ Less Power Dissipation

Description : What are four generations of Integration Circuits?

Last Answer : SSI (Small Scale Integration) _ MSI (Medium Scale Integration) _ LSI (Large Scale Integration) _ VLSI (Very Large Scale Integration)