Description : The ............... addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction. (A) Base indexed (B) Base indexed plus displacement (C) Indexed (D) Displacement
Last Answer : (D) Displacement
Description : Which one of the following is not an addressing mode? (A) Register indirect (B) Auto increment (C) Relative indexed (D) Immediate operand
Last Answer : (C) Relative indexed
Description : In which mode the main memory location holds the EA of the operand: a. Immediate addressing b. Direct addressing c. Register addressing d. Indirect addressing
Last Answer : d. Indirect addressing
Description : In post-indexing the contents of the address field are used to access a memory location containing a___ address: Immediate addressing Direct addressing Register addressing ao | None of these
Last Answer : Direct addressing
Description : In which addressing mode the operand is given explicitly in the instruction? A. Absolute B. Immediate C. Indirect D. Direct
Last Answer : B. Immediate
Description : The most common addressing techiniques employed by a CPU is a. immediate b. direct c. indirect d. register e. all of the above
Last Answer : e. all of the above
Description : In which addressing the operand is actually present in instruction: a. Immediate addressing b. Direct addressing 9 Register addressing a None of these
Last Answer : a. Immediate addressing
Description : Content of the program counter is added to the address part of the instruction in order to obtain the effective address is called_______ A. relative address mode. B. index addressing mode. C. register mode. D. implied mode.
Last Answer : A. relative address mode.
Description : In immediate addressing the operand is placed a. in the CPU register b. after OP code in the instruction c. in memory d. in stack
Last Answer : b. after OP code in the instruction
Description : In which addressing the simplest addressing mode where an operand is fetched from memory is a. Immediate addressing b. Direct addressing c. Register addressing d. None of these
Last Answer : b. Direct addressing
Description : In the indexed scheme of blocks to a file, the maximum possible size of the file depends on: (A) The number of blocks used for index, and the size of index (B) Size of Blocks and size of Address (C) Size of Index (D) Size of Block
Last Answer : (A) The number of blocks used for index, and the size of index
Description : System calls are usually invoked by using: (A) A privileged instruction (B) An indirect jump (C) A software interrupt (D) Polling
Last Answer : (C) A software interrupt
Description : Which of the following registers is used to keep track of address of the memory location where the next instruction is located? A) Memory address register B) Memory data register C) Instruction register D) Program counter
Last Answer : Answer : D
Description : Which of the following registers is loaded with the contents of the memory location pointed by the PC? A) Memory address registers B) Memory data registers C) Instruction register D) Program counter
Last Answer : Answer : C
Description : The load instruction is mostly used to designate a transfer from memory to a processor register known as_________ A. Accumulator B. Instruction Register C. Program counter D. Memory address Register
Last Answer : A. Accumulator
Description : The register which holds the address of the location to or from which data are to be transferred is known as_______ A. Instruction Register B. Control register C. Memory Address Register D. None of the Above
Last Answer : C. Memory Address Register
Description : The decoded instruction is stored in ______ (A) Register (B) Memory Address Register(MAR) (C) Instruction Register(IR) (D) None of the Above
Last Answer : (C) Instruction Register(IR)
Description : Which registers can interact with secondary memory? (A) Register (B) Memory Address Register(MAR) (C) Instruction Register(IR) (D) None of the Above
Last Answer : (B) Memory Address Register(MAR)
Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read
Last Answer : d. Address register and read
Description : The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, ... incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next
Last Answer : c. Instruction register, incremented and next
Description : Which of the following registers is used to keep track of address of the memory location where the next instruction is located? a. Memory address register b. Memory data register c. Instruction register d. Program counter
Last Answer : Program counter
Description : Which of the following registers is loaded with the contents of the memory location pointed by the PC? a. Memory address registers b. Memory data registers c. Instruction register d. Program counter
Last Answer : Instruction register
Description : The register which keeps track of the execution of a program and which contains the memory address of the instruction currently being executed is known as: a) Index Register b) Memory Address Register c) Program Counter d) None of The Above
Last Answer : c) Program Counter
Description : Which of the following registers is used to keep track of address of the memory location where the next instruction is located? a. Memory Address Register b. Memory Data Register c. Instruction Register d. Program Register
Last Answer : d. Program Register
Last Answer : d. Program counter
Description : Which of the following registers is loaded with the contents of the memory location pointed by the PC? a. Memory address register b. Memory data register c. Instruction registers d. Program counter
Last Answer : c. Instruction registers
Last Answer : c. Instruction register
Description : Suppose that the virtual Address space has eight pages and physical memory with four page frames. If LRU page replacement algorithm is used, .............. number of page faults occur with the reference string. 0 2 1 3 5 4 6 3 7 4 7 3 3 5 5 3 1 1 1 7 2 3 4 1 (A) 11 (B) 12 (C) 10 (D) 9
Last Answer : (A) 11
Description : In India, which is a comprehensive anti-discrimination law addressing all aspects of direct and indirect discrimination against women? a) Sexual Harassment of Women at Workplace (Prevention, Prohibition ... law c) National Commission for Women Act d) Protection of Women from Domestic Violence Act
Last Answer : b) There is no such law
Description : In classful addressing, the IP address 190.255.254.254 belongs to (A) Class A (B) Class B (C) Class C (D) Class D
Last Answer : (B) Class B
Description : In a classful addressing, first four bits in Class A IP address is (A) 1010 (B) 1100 (C) 1011 (D) 1110
Last Answer : Answer: A,B,C,D
Description : Which of the following is/are restriction(s) in classless addressing ? (A) The number of addresses needs to be a power of 2. (B) The mask needs to be included in the address to define the block. (C) The starting address must be divisible by the number of addresses in the block. (D) All of the above
Last Answer : (D) All of the above
Description : A CPU handles interrupt by executing interrupt service subroutine................. (A) by checking interrupt register after execution of each instruction (B) by checking interrupt register ... cycle (C) whenever an interrupt is registered (D) by checking interrupt register at regular time interval
Last Answer : (A) by checking interrupt register after execution of each instruction
Description : The contents of Register (BL) and Register (AL) of 8085 microprocessor are 49H and 3AH respectively. The contents of AL, the status of carry flag (CF) and sign flag (SF) after executing 'SUB AL, BL' assembly language instruction, are ( ... ; CF=0; SF=0 (3) AL=F1H; CF=1; SF=1 (4) AL=1FH; CF=1; SF=1
Last Answer : Answer: 3
Description : In length instruction some programs wants a complex instruction set containing more instruction, more addressing modes and greater address rang, as in case of a. RISC b. CISC c. Both d. None
Last Answer : b. CISC
Description : Assume a two address format specified as source, destination. Examine the following sequence of instruction and explain the addressing modes used and the operation done in every instruction?
Last Answer : 1. Move (R5) +, R0 2. Add (R5) +, R0. 3. Move (R0), (R5) 4. Move 16(R5), R3 5. Add #40, R5
Description : The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use memory bus. A memory read/write employs one machine cycle. For ... (A) 500 Kbytes/sec (B) 2.2 Mbytes/sec (C) 125 Kbytes/sec (D) 250 Kbytes/sec
Last Answer : (D) 250 Kbytes/sec
Description : Which addressing is an extremely influential way of addressing: a. Displacement addressing b. Immediate addressing 9 Direct addressing a Register addressing
Last Answer : a. Displacement addressing
Description : The final addressing mode that we consider is a. Immediate addressing b. Direct addressing c. Register addressing d. Stack addressing
Last Answer : d. Stack addressing
Description : Which addressing offset can be the content of PC and also can be negative: a. Relative addressing b. Immediate addressing c. Direct addressing d. Register addressing
Last Answer : a. Relative addressing
Description : A UNIX file system has 1 KB block size and 4-byte disk addresses. What is the maximum file size if the inode contains ten direct block entries, one single indirect block entry, one double indirect block entry and one triple indirect block entry? (A) 30 GB (B) 64 GB (C) 16 GB (D) 1 GB
Last Answer : (C) 16 GB
Description : A unix file system has 1-KB blocks and 4-byte disk addresses. What is the maximum file size if i-nodes contain 10 direct entries and one single, double and triple indirect entry each? (A) 32 GB (B) 64 GB (C) 16 GB (D) 1 GB
Description : Consider a program that consists of 8 pages (from 0 to 7) and we have 4 page frames in the physical memory for the pages. The page reference string is : 1 2 3 2 5 6 3 4 6 3 7 3 1 5 3 6 3 4 2 4 3 4 5 ... to fill available page frames with pages): (A) 9 and 6 (B) 10 and 7 (C) 9 and 7 (D) 10 and 6
Last Answer : (B) 10 and 7
Description : Computers can have instruction formats with (A) only two address and three address instructions (B) only one address and two address instructions (C) only one address, two address and three address instructions (D) zero address, one address, two address and three address instructions
Last Answer : (D) zero address, one address, two address and three address instructions
Description : Which instruction are arranged as per the protocols of memory reference format of the input file in a simple ASCII sequence of integers between the range O to 99 separated by spaces without formatted text ... : a. Memory reference instruction b. Memory reference format c. Both d. None of these
Last Answer : a. Memory reference instruction
Description : A byte addressable computer has a memory capacity of 2 m Kbytes and can perform 2 n operations. An instruction involving 3 operands and one operator needs a maximum of (A) 3m bits (B) m + n bits (C) 3m + n bits (D) 3m + n + 30 bits
Last Answer : (D) 3m + n + 30 bits
Description : Suppose that the number of instructions executed between page faults is directly proportional to the number of page frames allocated to a program. If the available memory is doubled, the mean interval between page faults is also ... memory were available? (A) 60 sec (B) 30 sec (C) 45 sec (D) 10 sec
Last Answer : Answer: C Explanation: T = Ninstr x 1µs + 15,000 x 2,000 µs = 60s Ninstr x 1µs = 60,000,000 µs - 30,000,000 µs = 30,000,000 µs Ninstr = 30,000,000 The number of instruction ... doesn't mean that the program runs twice as fast as on the first system. Here, the performance increase is of 25%.