Description : mplement W (A,B,C,D) = Ʃ (2,12,13)
Last Answer : X(A,B,C,D) = Ʃ (7,8,9,10,11,12,13,14,15) Y(A,B,C,D) = Ʃ (0,2,3,4,5,6,7,8,10,11,15) Z (A,B,C,D) = Ʃ (1,2,8,12,13) using PAL(16) • Table • PAL implementation
Description : . Define multiplexer?
Last Answer : Multiplexer is a digital switch. If allows digital information from several sources to be routed onto a single output line.
Description : Compute the value of adding the following two fuzzy integers: A = {(0.3,1), (0.6,2), (1,3), (0.7,4), (0.2,5)} B = {(0.5,11), (1,12), (0.5,13)} Where fuzzy addition is defined as μA+B(z) = maxx+y=z (min(μA(x), μB( ... ,18)} (D) {(0.3,12), (0.5,13), (0.6,14), (1,15), (0.7,16), (0.5,17), (0.2,18)}
Last Answer : (D) {(0.3,12), (0.5,13), (0.6,14), (1,15), (0.7,16), (0.5,17), (0.2,18)}
Description : Let A and B be two fuzzy integers defined as: A={(1,0.3), (2,0.6), (3,1), (4,0.7), (5,0.2)} B={(10,0.5), (11,1), (12,0.5)} Using fuzzy arithmetic operation given by (A) {(11,0.8), (13,1), (15,1)} ( ... ,0.2)} (D) {(11,0.3), (12,0.5), (13,0.6), (14,1), (15,0.7), (16,0.5), (17,0.2)}
Last Answer : (D) {(11,0.3), (12,0.5), (13,0.6), (14,1), (15,0.7), (16,0.5), (17,0.2)}
Description : A manufacture undertakes to supply 2000 pieces of a particular component at Rs.25 per piece. According to his estimates, even if 5% fail to pass the quality tests, then he will make a profit of 25%. However as it turned out, ... A. Rs 12,000 B. Rs 13,000 C. Rs 14,000 D. Rs 15,000 E. None f these
Last Answer : Answer - B. Rs 13,000 Explanation: 5% of 2000=100 so 2000-100=1900 so,if he sells 1900 he will get 25% profit cost per piece rs 25 so 25x 1900 don't solve here if 125% . ... /125=38000=CP if 50% rejected,only 1000 pieces sold so 1000 25=25000=SP loss=cp-sp= 38000-25000=13000
Description : I have some matchsticks set up like this: I + XI = X. If you do not know Roman numerals, here is a quick starter: I=1 II=2 III=3 IV=4 V=5 VI=6 VII=7 VIII=8 IX=9 X=10 XI=11 ... are told to move the minimum number of matchsticks to make the question correct. So, how many do you have to move? -Riddles
Last Answer : Most people would get to one move at the least, but the real answer is zero moves. If you rotate the whole question around 180 degrees, it will display this: X = IX + I
Description : 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50'. What number is missing? -Riddles
Last Answer : 22
Description : the range of the data 13, 18, 20, 15, 12, 17, 9, 14, 11, and 16 is ________.
Last Answer : the range of the data 13, 18, 20, 15, 12, 17, 9, 14, 11, and 16 is ________.
Description : 2. Arrange the following fractions in ascending order:(i) \( \frac{3}{8}, \frac{5}{6}, \frac{6}{8}, \frac{2}{4}, \frac{1}{3} \)(ii) \( \frac{4}{6}, \frac{3}{8}, \frac{6}{12}, \frac{5}{16} \)3. Arrange the ... ( \frac{23}{3} \) and 6(iii) \( \frac{18}{20} \) and \( \frac{21}{25} \)(iv) \( 3 \frac{3
Last Answer : 2. Arrange the following fractions in ascending order: (i) \( \frac{3}{8}, \frac{5}{6}, \frac{6}{8}, \frac ... frac{3}{10} \) and \( 2 \frac{7}{15} \)
Description : What are the common factors of 11 12 13 14 and 15?
Last Answer : 1 is a common factor of 11, 12, 13, 14 and 15.
Description : What is the output of the following? i = 5 while True: if i%0O9 == 0: break print(i) i += 1 a) 5 6 7 8 b) 5 6 7 8 9 c) 5 6 7 8 9 10 11 12 13 14 15 …. d) error
Last Answer : d) error
Description : In each of the following questions, find the odd number/letters/word from the given alternatives. 10. (a) PQXZ (b) BCQN (c) ABDF (d) MNPR 11. (a) ABYZ (b) CDWX (c) EFUV (d) GHTV 12. ... ) Sailing (c) Dividing (d) Driving 15. (a) Perception (b) Discernment (c) Penetration (d) Insinuation
Last Answer : 10. (b) 11. (d) 12. (b) 13. (d) 14. (d) 15. (d)
Description : Two students appeared at an examination. One of them secured 18marks more than the other and his marks was 72% of the sum of their marks. What are the marks obtained by them? a) 12.5,23.3 b) 26.7,16.0 c) 13.3,14.2 d) 11.45, 29.45 e) 29.8,15.4
Last Answer : Answer: D Let the marks secured by them be x and (x + 18) Then sum of their marks = x + (x + 18) = 2x + 18 Given that (x + 18) was 72% of the sum of their marks =>(x+18) = 72/100(2x+18) => ... 11x = 126 x = 11.45 Then (x + 18) = 11.45 + 18 = 29.45 Hence their marks are 11.45 and 29.45
Description : Explain the different methods of state assignment
Last Answer : • Three row state assignment • Shared row state assignment • Four row flow table • Multiple row state assignment • Prevention of races can happen only when S=0 and R=1.
Description : Explain in detail about Races.
Last Answer : • Basics of races • Problem created due to races • Classification of races • Remedy for races • cycles
Description : Design a asynchronous sequential circuit with 2 inputs T and C. The output attains a value of 1 when T = 1 & c moves from 1 to 0. Otherwise the output is 0
Last Answer : • Obtain the state diagram • Obtain the flow table • Using implication table reduce the flow table • Using merger graph obtain maximal compatibles • Verify closed & covered conditions • Plot the reduced flow table • Obtain transition table • Excitation table • Logic diagram
Description : State with a neat example the method for the minimization of primitive flow table.
Last Answer : • Consider a state diagram • Obtain the flow table • Using implication table reduce the flow table • Using merger graph obtain maximal compatibles • Verify closed & covered conditions • Plot the reduced flow table
Description : Explain with neat diagram the different hazards and the way to eliminate them.
Last Answer : • Classification of hazards • Static hazard & Dynamic hazard definitions • K map for selected functions • Method of elimination • Essential hazards
Description : Explain in detail about serial in serial out shift register.
Last Answer : • Block diagram • Theoretical explanation • Logic diagram • Working
Description : Design a sequential detector which produces an output 1 every time the input sequence 1011 is detected.
Last Answer : • Construct state diagram • Obtain the flow table • Obtain the flow table & output table • Transition table • Select flip flop • Excitation table
Description : Explain the working of BCD Ripple Counter with the help of state diagram and logic diagram.
Last Answer : • BCD Ripple Counter Count sequence • Truth Table • State diagram representing the Truth Table • Truth Table for the J-K Flip Flop • Logic Diagram
Description : Explain in detail about PLA and PAL.
Last Answer : • Logic difference between Prom & PLA • Logic diagram implementing a function • Logic difference between Prom & PAL • Logic diagram implementing a function
Description : Design a logic circuit to convert the BCD code to Excess –
Last Answer : code. • Truth Table for BCD to Excess – 3 conversion. • K-map simplification • Logic circuit implementing the Boolean Expression
Description : Explain in detail the look ahead carry generator.
Last Answer : • Block diagram • Explanation • Logic diagram
Description : Design and explain a comparator to compare two identical
Last Answer : words. • Two numbers represented by A = A3A2A1A0 & B = B3B2B1B0 • If two numbers equal P = Ai Bi • Obtain the logic Expression. • Obtain the logic diagram.
Description : Explain the flip-flop excitation tables for RS FF.
Last Answer : • RS flip-flop • In RS flip-flop there are four possible transitions from the present state to the next state. They are, • 0 0 transition: This can happen either when R=S=0 or when R=1 and S=0. • 0 1 transition: This can happen only when S=1 and R=0. • 1 0 transition: This
Description : What are the different types of shift type?
Last Answer : There are five types. They are, Serial In Serial Out Shift Register Serial In Parallel Out Shift Register Parallel In Serial Out Shift Register Parallel In Parallel Out Shift Register Bidirectional Shift Register
Description : Define shift registers.
Last Answer : Define shift registers.
Description : Define registers.
Last Answer : A register is a group of flip-flops flip-flop can store one bit information. So an n bit register has a group of n flip-flops and is capable of storing any binary information/number containing n-bits.
Description : Define propagation delay.
Last Answer : A propagation delay is the time required to change the output after the application of the input.
Description : Define hold time.
Last Answer : The hold time is the minimum time for which the voltage levels at the excitation inputs must remain constant after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as thold .
Description : Define setup time.
Last Answer : The setup time is the minimum time required to maintain a constant voltage levels at the excitation inputs of the flip-flop device prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is denoted as tsetup.
Description : Define skew and clock skew
Last Answer : The phase shift between the rectangular clock waveforms is referred to as skew and the time delay between the two clock pulses is called clock skew.
Description : Define fall time.
Last Answer : The time required to change the voltage level from 90% to 10% is known as fall time(tf).
Description : Define rise time.
Last Answer : The time required to change the voltage level from 10% to 90% is known as rise time(tr).
Description : What is a master-slave flip-flop?
Last Answer : A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.
Description : What is edge-triggered flip-flop?
Last Answer : The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock.
Description : Define race around condition.
Last Answer : In JK flip-flop output is fed back to the input. Therefore change in the output results change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition is called ‘race around condition’.
Description : What is the operation of T flip-flop?
Last Answer : T flip-flop is also known as Toggle flip-flop. • When T=0 there is no change in the output. • When T=1 t
Description : What is the operation of JK flip-flop?
Last Answer : When K input is low and J input is high the Q output of flip-flop is set. When K input is high and J input is low the Q output of flip-flop is reset. When both the inputs K and ... are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.
Description : What is the operation of D flip-flop?
Last Answer : In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.
Description : What are the different types of flip-flop?
Last Answer : There are various types of flip flops. Some of them are mentioned below they are, 1. RS flip-flop 2. SR flip-flop 3. D flip-flop 4. JK flip-flop 5. T flip-flop
Description : Define Flip flop.
Last Answer : The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state.
Description : What are the classifications of sequential circuits?
Last Answer : The sequential circuits are classified on the basis of timing of their signals into two types. They are, 1) Synchronous sequential circuit. 2) Asynchronous sequential circuit.
Description : Give the comparison between PROM and PLA.
Last Answer : PROM PLA 1. And array is fixed and OR Both AND and OR arrays are array is programmable. Programmable. 2. Cheaper and simple to use. Costliest and complex than PROMS.
Description : What does PAL 10L8 specify?
Last Answer : PAL - Programmable Logic Array 10 - Ten inputs L - Active LOW Output 8 - Eight Outputs
Description : Why the input variables to a PAL are buffered
Last Answer : The input variables to a PAL are buffered to prevent loading by the large number of AND gate inputs to which available or its complement can be connected.
Description : Why was PAL developed?
Last Answer : It is a PLD that was developed to overcome certain disadvantages of PLA, such as longer delays due to additional fusible links that result from using two programmable arrays and more circuit complexity.
Description : Define PROM.
Last Answer : PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates connected to a decoder and a programmable OR array.
Description : Define PLD.Give the classification of PLDs.
Last Answer : PLDs are classified as PROM (Programmable Read Only Memory), Programmable Logic Array (PLA), Programmable Array Logic (PAL), and Generic Array Logic (GAL)