Block diagram of DM transmitter:-
Explanation:-
Sample and Hold:- The input analog is sampled and converted to PAM signal, which is compared with the output of the DAC. The output of the DAC is a voltage equal to the regenerated magnitude of the previous sample, which was stored in the up-down counter as a binary number.
Up-down counter:- The up-down counter is incremented or decremented depending on whether the previous sample is larger or smaller than the current sample. The up-down counter is clocked at a rate equal to the sample rate. Therefore the up-down counter is updated after each comparison. Initially the up-down counter is zeroed and DAC output is 0v. The first sample is taken and converted to a PAM signal, and compared with zero volts. The output of the comparator is a logic 1 condition (+v), indcating that the current sample is larger in amplitude than the previous sample. On the next clock pulse, the up- down counter is incremented to a count of 1.The DAC now outputs a voltage equal to the mgnitude of the minimum step size (resolution). The steps change at a rate equal to the clock frequency (sample rate). Consequently, with the input signal shown, the up-down counter follows the input analog signal up until the output of the DAC exceeds the analog sample; then the up-down counter will begin counting down until the output of the DAC drops below th sample amplitude.
Digital to Analog Converter (DAC):- In the idealized situation the DAC output follows the input signal. Each time the up-down counter is incremented, a logic 1 is transmitted, and each time the up-down counter is decremented, alogic 0 is transmitted.
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