The virtual address generated by a CPU is 32 bits. The Translation Lookaside Buffer (TLB) can hold total 64 page table entries and a 4-way set associative (i.e. with 4- cache lines in the set). The page size is 4 KB. The minimum size of TLB tag is (A) 12 bits (B) 15 bits (C) 16 bits (D) 20 bits

The virtual address generated by a CPU is 32 bits. The Translation Lookaside Buffer (TLB) can hold total 64 page table entries and a 4-way set associative (i.e. with 4- cache lines in the set). The page size is 4 KB. The minimum size of TLB tag is (A) 12 bits (B) 15 bits (C) 16 bits (D) 20 bits
by

1 Answer

Answer :

(C) 16 bits

Explanation:

VirtualAddress = 32 bits

PageSize = 4KB = 12 bits

therefore : VPNTag = 20 bits, OffsetTag = 12 bits

TLBEntryLength = VPNTag = 20 bits

TotalTLBEntries = 64,

4-way implies 64/ 4 = 16 sets = 4 bits

therefore : TLBIndex = 4 bits


TLBTag = TLBEntryLength - TLBIndex = 20 - 4 = 16 bits
by

Related questions

Translation Look-aside Buffer(TLB) is (A) a cache-memory in which item to be searched is compared one-by-one with the keys. (B) a cache-memory in which item to be searched is compared with all the keys simultaneously. (C) an associative memory in which item to be searched is compared one-by-one with the keys. (D) an associative memory in which item to be searched is compared with all the keys simultaneously.

Description : Translation Look-aside Buffer(TLB) is (A) a cache-memory in which item to be searched is compared one-by-one with the keys. (B) a cache-memory in which item to be searched is compared with ... keys. (D) an associative memory in which item to be searched is compared with all the keys simultaneously.

Last Answer : (D) an associative memory in which item to be searched is compared with all the keys simultaneously.

A virtual memory has a page size of 1K words. There are eight pages and four blocks. The associative memory page table contains the following entries: Image Which of the following list of virtual addresses (in decimal) will not cause any page fault if referenced by the CPU? (A) 1024, 3072, 4096, 6144 (B) 1234, 4012, 5000, 6200 (C) 1020, 3012, 6120, 8100 (D) 2021, 4050, 5112, 7100

Description : A virtual memory has a page size of 1K words. There are eight pages and four blocks. The associative memory page table contains the following entries:  Which of the following list of virtual addresses (in ... 1234, 4012, 5000, 6200 (C) 1020, 3012, 6120, 8100 (D) 2021, 4050, 5112, 7100

Last Answer : Answer: C Explanation: The pages which are not in main memory are: 1020 will not cause page fault (1024-2047) 3012 will not cause page fault (3072-4095) 6120 will not cause page fault (4096-5119) 8100 will not cause page fault (6144-7167)

Define Translation-Lookaside Buffer (TLB)?

Description : Define Translation-Lookaside Buffer (TLB)?

Last Answer : Most commercial virtual memory systems incorporate a mechanism that can avoid the bulk of the main memory access called for by the virtual to physical addresses translation buffer. This may be done with a cache memory called a translation buffer, which retains the results of the recent translation.

A unix file system has 1-KB blocks and 4-byte disk addresses. What is the maximum file size if i-nodes contain 10 direct entries and one single, double and triple indirect entry each? (A) 32 GB (B) 64 GB (C) 16 GB (D) 1 GB

Description : A unix file system has 1-KB blocks and 4-byte disk addresses. What is the maximum file size if i-nodes contain 10 direct entries and one single, double and triple indirect entry each? (A) 32 GB (B) 64 GB (C) 16 GB (D) 1 GB

Last Answer : (C) 16 GB

A memory management system has 64 pages with 512 bytes page size. Physical memory consists of 32 page frames. Number of bits required in logical and physical address are respectively: (1) 14 and 15 (2) 14 and 29 (3) 15 and 14 (4) 16 and 32

Description : A memory management system has 64 pages with 512 bytes page size. Physical memory consists of 32 page frames. Number of bits required in logical and physical address are respectively: (1) 14 and 15 (2) 14 and 29 (3) 15 and 14 (4) 16 and 32

Last Answer : (3) 15 and 14

What is the most appropriate function of Memory Management Unit (MMU) ? (A) It is an associative memory to store TLB (B) It is a technique of supporting multiprogramming by creating dynamic partitions (C) It is a chip to map virtual address to physical address (D) It is an algorithm to allocate and deallocate main memory to a process

Description : What is the most appropriate function of Memory Management Unit (MMU) ? (A) It is an associative memory to store TLB (B) It is a technique of supporting multiprogramming by creating dynamic partitions ... to physical address (D) It is an algorithm to allocate and deallocate main memory to a process 

Last Answer : (C) It is a chip to map virtual address to physical address

A UNIX file system has 1 KB block size and 4-byte disk addresses. What is the maximum file size if the inode contains ten direct block entries, one single indirect block entry, one double indirect block entry and one triple indirect block entry? (A) 30 GB (B) 64 GB (C) 16 GB (D) 1 GB

Description : A UNIX file system has 1 KB block size and 4-byte disk addresses. What is the maximum file size if the inode contains ten direct block entries, one single indirect block entry, one double indirect block entry and one triple indirect block entry? (A) 30 GB (B) 64 GB (C) 16 GB (D) 1 GB

Last Answer : (C) 16 GB

In a paging system, it takes 30 ns to search translation Look-aside Buffer (TLB) and 90 ns to access the main memory. If the TLB hit ratio is 70%, the effective memory access time is: (1) 48 ns (2) 147 ns (3) 120 ns (4) 84 ns

Description : In a paging system, it takes 30 ns to search translation Look-aside Buffer (TLB) and 90 ns to access the main memory. If the TLB hit ratio is 70%, the effective memory access time is: (1) 48 ns (2) 147 ns (3) 120 ns (4) 84 ns

Last Answer : Answer: 2

The IEEE-754 double-precision format to represent floating point numbers, has a length of ........... bits. (A) 16 (B) 32 (C) 48 (D) 64

Description : The IEEE-754 double-precision format to represent floating point numbers, has a length of ........... bits. (A) 16 (B) 32 (C) 48 (D) 64

Last Answer : (D) 64

The directory can be viewed as .................... that translates filenames into their directory entries. (A) Symbol table (B) Partition (C) Swap space (D) Cache

Description : The directory can be viewed as .................... that translates filenames into their directory entries. (A) Symbol table (B) Partition (C) Swap space (D) Cache

Last Answer : (A) Symbol table

What is the size of the 'total length' field in IPv 4 datagram ? (A) 4 bits (B) 8 bits (C) 16 bits (D) 32 bits

Description : What is the size of the 'total length' field in IPv 4 datagram ? (A) 4 bits (B) 8 bits (C) 16 bits (D) 32 bits

Last Answer : (C) 16 bits 

Function of memory management unit is : (A) Address translation (B) Memory allocation (C) Cache management (D) All of the above

Description : Function of memory management unit is : (A) Address translation (B) Memory allocation (C) Cache management (D) All of the above

Last Answer : Answer: A

How many bits internet address isassigned to eachhost on a TCP/IP internet which is used in all communications withthehost? A. 16 - bits B. 32 - bits C. 48 - bits D. 64 - bits E. None of the above

Description : How many bits internet address isassigned to eachhost on a TCP/IP internet which is used in all communications withthehost? A. 16 - bits B. 32 - bits C. 48 - bits D. 64 - bits E. None of the above

Last Answer : 32 - bits

The processor 80386/80486 and the Pentium processor uses _____ bits address bus: a. 16 b. 32 c. 36 d. 64

Description : The processor 80386/80486 and the Pentium processor uses _____ bits address bus: a. 16 b. 32 c. 36 d. 64

Last Answer : b. 32

In IT, associative memory is called as (1) Virtual memory (2) Cache memory (3) Content addressable memory (4) Main memory

Description : In IT, associative memory is called as (1) Virtual memory (2) Cache memory (3) Content addressable memory (4) Main memory

Last Answer : Content addressable memory

In hierarchical routing with 4800 routers, what region and cluster sizes should be chosen to minimize the size of the routing table for a three layer hierarchy? (A) 10 clusters, 24 regions and 20 routers (B) 12 clusters, 20 regions and 20 routers (C) 16 clusters, 12 regions and 25 routers (D) 15 clusters, 16 regions and 20 routers

Description : In hierarchical routing with 4800 routers, what region and cluster sizes should be chosen to minimize the size of the routing table for a three layer hierarchy? (A) 10 clusters, 24 regions and 20 routers (B ... (C) 16 clusters, 12 regions and 25 routers (D) 15 clusters, 16 regions and 20 routers

Last Answer : (D) 15 clusters, 16 regions and 20 routers Rooters minimum, then regions minimum, then clusters minimum.

Registers which are partially visible to users and used to hold conditional codes (bits set by the CPU hardware as the result of operations), are known as A) PC B) Flags C) Memory Address Registers D) General Purpose Registers

Description : Registers which are partially visible to users and used to hold conditional codes (bits set by the CPU hardware as the result of operations), are known as A) PC B) Flags C) Memory Address Registers D) General Purpose Registers

Last Answer : Answer : B

What is size of the IPv6 Address? A. 32 bits B. 64 bits C. 128 bits D. 256 bits

Description : What is size of the IPv6 Address? A. 32 bits B. 64 bits C. 128 bits D. 256 bits

Last Answer : C. 128 bits 

Suppose a digitized voice channel is made by digitizing 8 kHz bandwidth analog voice signal. It is required to sample the signal at twice the highest frequency (two samples per hertz). What is the bit rate required, if it is assumed that each sample requires 8 bits? (A) 32 kbps (B) 64 kbps (C) 128 kbps (D) 256 kbps

Description : Suppose a digitized voice channel is made by digitizing 8 kHz bandwidth analog voice signal. It is required to sample the signal at twice the highest frequency (two samples per hertz). What is the bit rate required, if it ... sample requires 8 bits? (A) 32 kbps (B) 64 kbps (C) 128 kbps (D) 256 kbps

Last Answer : (C) 128 kbps

If link transmits 4000 frames per second and each slot has 8 bits, the transmission rate of circuit of this TDM is ............... (A) 64 Kbps (B) 32 Mbps (C) 32 Kbps (D) 64 Mbps

Description : If link transmits 4000 frames per second and each slot has 8 bits, the transmission rate of circuit of this TDM is ............... (A) 64 Kbps (B) 32 Mbps (C) 32 Kbps (D) 64 Mbps

Last Answer : (C) 32 Kbps

Suppose that the virtual Address space has eight pages and physical memory with four page frames. If LRU page replacement algorithm is used, .............. number of page faults occur with the reference string. 0 2 1 3 5 4 6 3 7 4 7 3 3 5 5 3 1 1 1 7 2 3 4 1 (A) 11 (B) 12 (C) 10 (D) 9

Description : Suppose that the virtual Address space has eight pages and physical memory with four page frames. If LRU page replacement algorithm is used, .............. number of page faults occur with the reference string. 0 2 1 3 5 4 6 3 7 4 7 3 3 5 5 3 1 1 1 7 2 3 4 1 (A) 11 (B) 12 (C) 10 (D) 9

Last Answer : (A) 11

IPv4 and IPv6 are addresses used to identify computers on the internet. Find the correct statement out of the following: (A) Number of bits required for IPv4 address is more than number of bits required for IPv6 address. (B) Number of bits required for IPv4 address is same as number of bits required for IPv6 address. (C) Number of bits required for IPv4 address is less than number of bits required for IPv6 address. (D) Number of bits required for IPv4 address is 64.

Description : IPv4 and IPv6 are addresses used to identify computers on the internet. Find the correct statement out of the following: (A) Number of bits required for IPv4 address is more than number of bits required for ... of bits required for IPv6 address. (D) Number of bits required for IPv4 address is 64. 

Last Answer : (C) Number of bits required for IPv4 address is less than number of bits required for IPv6 address.

A data file of 1,00,000 characters contains only the characters g-l, with the frequencies as indicated in table: using the variable-length code by Huffman codes, the file can be encoded with (A) 2,52,000 bits (B) 2,64,000 bits (C) 2,46,000 bits (D) 2,24,000 bits

Description : A data file of 1,00,000 characters contains only the characters g-l, with the frequencies as indicated in table:  using the variable-length code by Huffman codes, the file can be encoded with (A) 2,52,000 bits (B) 2,64,000 bits (C) 2,46,000 bits (D) 2,24,000 bits

Last Answer : (D) 2,24,000 bits 

Station A uses 32 byte packets to transmit messages to station B using sliding window protocol. The round trip delay between A and B is 40 milli seconds and the bottleneck bandwidth on the path between A and B is 64 kbps. The optimal window size of A is (1) 20 (2) 10 (3) 30 (4) 40

Description : Station A uses 32 byte packets to transmit messages to station B using sliding window protocol. The round trip delay between A and B is 40 milli seconds and the bottleneck bandwidth on the path between A and B is 64 kbps. The optimal window size of A is (1) 20 (2) 10 (3) 30 (4) 40

Last Answer : (2) 10

Four bits are used for packed sequence numbering in a sliding window protocol used in a computer network. What is the maximum window size ? (A) 4 (B) 8 (C) 15 (D) 16

Description : Four bits are used for packed sequence numbering in a sliding window protocol used in a computer network. What is the maximum window size ?  (A) 4 (B) 8 (C) 15 (D) 16

Last Answer : (C) 15 

Assume that we need to download text documents at the rate of 100 pages per minute. A page is an average of 24 lines with 80 characters in each line and each character requires 8 bits. Then the required bit rate of the channel is ................ (A) 1.636 Kbps (B) 1.636 Mbps (C) 2.272 Mbps (D) 3.272 Kbps

Description : Assume that we need to download text documents at the rate of 100 pages per minute. A page is an average of 24 lines with 80 characters in each line and each character requires 8 bits. Then the required bit rate of the channel is ... ...... (A) 1.636 Kbps (B) 1.636 Mbps (C) 2.272 Mbps (D) 3.272 Kbps

Last Answer : Answer: Marks given to all

Consider a subnet with 720 routers. If a three-level hierarchy is choosen with eight clusters, each containing 9 regions of 10 routers, then total number of entries in the routing table is ................... (A) 25 (B) 27 (C) 53 (D) 72

Description : Consider a subnet with 720 routers. If a three-level hierarchy is choosen with eight clusters, each containing 9 regions of 10 routers, then total number of entries in the routing table is ................... (A) 25 (B) 27 (C) 53 (D) 72

Last Answer : Answer: A  Explanation: Each router needs 10 entries for local routers, 8 entries for routing to other regions within its own cluster, and 7 entries for distant clusters, for a total of 25 entries.

How many address bits are required to represent a 32 K memory (A) 10 bits. (B) 12 bits. (C) 14 bits. (D) 16 bits.

Description : How many address bits are required to represent a 32 K memory (A) 10 bits. (B) 12 bits. (C) 14 bits. (D) 16 bits.

Last Answer : (D) 16 bits.

An IPv4 address consistsof _______ bits. A) 4 B) 8 C) 32 D) 64

Description : An IPv4 address consistsof _______ bits. A) 4 B) 8 C) 32 D) 64

Last Answer : 32

An IPv6 address is _________ bits long A. 32 B. 64 C. 128 D. none of the above

Description : An IPv6 address is _________ bits long A. 32 B. 64 C. 128 D. none of the above

Last Answer : C. 128

What is the size of an IP address? A. 64 bit B. 128 bit C. 16 bit D. 32 bit

Description : What is the size of an IP address? A. 64 bit B. 128 bit C. 16 bit D. 32 bit

Last Answer : D. 32 bit

Windows 32 API supports (A) 16-bit Windows (B) 32-bit Windows (C) 64-bit Windows (D) All of the above

Description : Windows 32 API supports (A) 16-bit Windows (B) 32-bit Windows (C) 64-bit Windows (D) All of the above

Last Answer : (D) All of the above

In a demand paging memory system, page table is held in registers. The time taken to service a page fault is 8 m.sec. if an empty frame is available or if the replaced page is not modified, and it takes 20 m.secs., if the replaced page is modified. What is the average access time to service a page fault assuming that the page to be replaced is modified 70% of the time ? (A) 11.6 m.sec. (B) 16.4 m.sec. (C) 28 m.sec. (D) 14 m.sec.

Description : In a demand paging memory system, page table is held in registers. The time taken to service a page fault is 8 m.sec. if an empty frame is available or if the replaced page is not modified, and it takes 20 m.secs., if the replaced ... ? (A) 11.6 m.sec. (B) 16.4 m.sec. (C) 28 m.sec. (D) 14 m.sec.

Last Answer : (B) 16.4 m.sec. 

The Internet addresses are ______ bits in length in IPV4 addressing scheme A. 16 B. 64 C. 32 D. 48

Description : The Internet addresses are ______ bits in length in IPV4 addressing scheme A. 16 B. 64 C. 32 D. 48

Last Answer : C. 32

The Internet addresses are ……….. bits in length in IPV4 addressing scheme a. 16 b. 64 c. 48 d. 32

Description : The Internet addresses are ……….. bits in length in IPV4 addressing scheme a. 16 b. 64 c. 48 d. 32

Last Answer : d. 32

Consider the following justifications for commonly using the two-level CPU scheduling : I. It is used when memory is too small to hold all the ready processes. II. Because its performance is same as that of the FIFO. III. Because it facilitates putting some set of processes into memory and a choice is made from that. IV. Because it does not allow to adjust the set of in-core processes. Which of the following is true ? (A) I, III and IV (B) I and II (C) III and IV (D) I and III

Description : Consider the following justifications for commonly using the two-level CPU scheduling : I. It is used when memory is too small to hold all the ready processes. II. Because its performance is same as that of the FIFO. III. Because it ... ? (A) I, III and IV (B) I and II (C) III and IV (D) I and III

Last Answer : (D) I and III

___________ is a very high speed memory placed in between RAM and CPU. A. Magnetic disk B. Magnetic drum C. Virtual memory D. Cache memory

Description : ___________ is a very high speed memory placed in between RAM and CPU. A. Magnetic disk B. Magnetic drum C. Virtual memory D. Cache memory

Last Answer : D. Cache memory

Let the page fault service time be 10 millisecond(ms) in a computer with average memory access time being 20 nanosecond(ns). If one page fault is generated for every 106 memory accesses, what is the effective access time for memory? (A) 21 ns (B) 23 ns (C) 30 ns (D) 35 ns

Description : Let the page fault service time be 10 millisecond(ms) in a computer with average memory access time being 20 nanosecond(ns). If one page fault is generated for every 106 memory accesses, what is the effective access time for memory? (A) 21 ns (B) 23 ns (C) 30 ns (D) 35 ns

Last Answer : (C) 30 ns

For the implementation of a paging scheme, suppose the average process size be x bytes, the page size be y bytes, and each page entry requires z bytes. The optimum page size that minimizes the total overhead due to the page table and the internal fragmentation loss is given by (A) x/2 (B) xz/2 (C) √2xz (D) (√xz)/2

Description : For the implementation of a paging scheme, suppose the average process size be x bytes, the page size be y bytes, and each page entry requires z bytes. The optimum page size that minimizes the total overhead due to the page ... fragmentation loss is given by (A) x/2 (B) xz/2 (C) √2xz (D) (√xz)/2

Last Answer : (C) √2xz 

A dynamic RAM has refresh cycle of 32 times per msec. Each refresh operation requires 100 nsec and a memory cycle requires 250 nsec. What percentage of memory’s total operating time is required for refreshes? (A) 0.64 (B) 0.96 (C) 2.00 (D) 0.32

Description : A dynamic RAM has refresh cycle of 32 times per msec. Each refresh operation requires 100 nsec and a memory cycle requires 250 nsec. What percentage of memory’s total operating time is required for refreshes? (A) 0.64 (B) 0.96 (C) 2.00 (D) 0.32

Last Answer : Answer: D Explanation: in 1ms : refresh = 32 times Memory cycle = 1ms/250ns = 106ns/250ns = 4000 times Therefore, % of refresh time = (32 x 100ns)/(4000 x 250ns) = 3200ns/1000000 x 100% = 0.32%

Consider a source with symbols A, B, C, D with probabilities 1/2, 1/4, 1/8, 1/8 respectively. What is the average number of bits per symbol for the Huffman code generated from above information? (A) 2 bits per symbol (B) 1.75 bits per symbol (C) 1.50 bits per symbol (D) 1.25 bits per symbol

Description : Consider a source with symbols A, B, C, D with probabilities 1/2, 1/4, 1/8, 1/8 respectively. What is the average number of bits per symbol for the Huffman code generated from above information? (A) 2 bits per symbol (B) 1.75 bits per symbol (C) 1.50 bits per symbol (D) 1.25 bits per symbol

Last Answer : (B) 1.75 bits per symbol

Consider the following statements: (a) Revised simplex method requires lesser computations than the simplex method. (b) Revised simplex method automatically generates the inverse of the current basis matrix. (c) Less number of entries are needed in each table of revised simplex method than usual simplex method. Which of these statements are correct? (A) (a) and (b) only (B) (a) and (c) only (C) (b) and (c) only (D) (a), (b) and (c)

Description : Consider the following statements: (a) Revised simplex method requires lesser computations than the simplex method. (b) Revised simplex method automatically generates the inverse of the current basis matrix. (c) Less number of entries are needed ... c) only (C) (b) and (c) only (D) (a), (b) and (c)

Last Answer : (D) (a), (b) and (c)

A typical personal computer used for business purposes would have of RAM. A) 4 KB B) 16 K C) 64 K D) 256 K

Description : A typical personal computer used for business purposes would have of RAM. A) 4 KB B) 16 K C) 64 K D) 256 K

Last Answer : Answer : D

A typical personal computer used for business purposes would have… of RAM. a. 4 KB b. 16 K c. 64 K d. 256 K

Description : A typical personal computer used for business purposes would have… of RAM. a. 4 KB b. 16 K c. 64 K d. 256 K

Last Answer : d. 256 K

A typical personal computer used for business purposes would have… of RAM. a. 4 KB b. 16 K c. 64 K d. 256 K

Description : A typical personal computer used for business purposes would have… of RAM. a. 4 KB b. 16 K c. 64 K d. 256 K

Last Answer : d. 256 K

A memory unit stores 2^16 bytes in 32-bit words. How many address bits are necessary in order to retrieve a single word from this memory unit?

Description : A memory unit stores 2^16 bytes in 32-bit words. How many address bits are necessary in order to retrieve a single word from this memory unit?

Last Answer : Each word is 4 bytes, which occupies 4 consecutive addresses at 16 bits each. The first 14 bits of these addresses will be the same, differing only in the two least significant bits. You only need to specify the first 14 bits, because there are only 2^14 words occupying those 2^16 bytes.

Given the symbols A, B, C, D, E, F, G and H with the probabilities 1/30, 1/30, 1/30, 2/30, 3/30, 5/30, 5/30 and 12/30 respectively. The average Huffman code size in bits per symbol is: (A) 67/30 (B) 70/34 (C) 76/30 (D) 78/30

Description : Given the symbols A, B, C, D, E, F, G and H with the probabilities 1/30, 1/30, 1/30, 2/30, 3/30, 5/30, 5/30 and 12/30 respectively. The average Huffman code size in bits per symbol is: (A) 67/30 (B) 70/34 (C) 76/30 (D) 78/30

Last Answer : (C) 76/30

How much space will be required to store the bit map of a 1.3 GB disk with 512 bytes block size ? (A) 332.8 KB (B) 83.6 KB (C) 266.2 KB (D) 256.6 KB

Description : How much space will be required to store the bit map of a 1.3 GB disk with 512 bytes block size ? (A) 332.8 KB (B) 83.6 KB (C) 266.2 KB (D) 256.6 KB

Last Answer : (A) 332.8 KB

The order of a leaf node in a B+ tree is the maximum number of children it can have. Suppose that block size is 1 kilobytes, the child pointer takes 7 bytes long and search field value takes 14 bytes long. The order of the leaf node is ............ (1) 16 (2) 63 (3) 64 (4) 65

Description : The order of a leaf node in a B+ tree is the maximum number of children it can have. Suppose that block size is 1 kilobytes, the child pointer takes 7 bytes long and search field value takes 14 bytes long. The order of the leaf node is ............ (1) 16 (2) 63 (3) 64 (4) 65

Last Answer : Answer: All

Consider a 32 - bit microprocessor, with a 16 - bit external data bus, driven by an 8 MHz input clock. Assume that the microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate for this microprocessor? (A) 8x106 bytes/sec (B) 4x106 bytes/sec (C) 16x106 bytes/sec (D) 4x109 bytes/sec

Description : Consider a 32 - bit microprocessor, with a 16 - bit external data bus, driven by an 8 MHz input clock. Assume that the microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What ... (A) 8x106 bytes/sec (B) 4x106 bytes/sec (C) 16x106 bytes/sec (D) 4x109 bytes/sec 

Last Answer : (B) 4x106 bytes/sec