Fig shows the circuit diagram of an unbiased positive diode clamper.
fig shows the input waveform applied to the positive diode clamper.
During the negative half cycle of the A.C. input signal Vi, the diode D is forward biased and current flows through the circuit.
The diode D acts as a short- circuit, i.e closed series switch and the capacitor C is charged to a voltage equal to the negative peak voltage –Vm.
Once the capacitor is C is fully charged to –Vm, it is not discharged because the diode D cannot conduct in reverse bias condition.
Now the capacitor C stores the charge and acts as a battery with an e.m.f equal to –Vm.
The polarity of this voltage is such that it adds to the positive half cycle of the input signal. So the output voltage is equal to the sum of the input voltage Vi and the capacitor voltage Vm. The output will be given by,
Vo=Vi+Vm=Vmsinwt + Vm.
The input signal voltage at the output becomes twice the peak voltage of the input signal.
The output signal will make excursion between zero level and +2Vm of the input signal.This causes the input signal to clamp positively at 0V,i.e. negative peak is clamped at zero level as shown in fig.
Diagram-
Operation
In the first negative half cycle after turning on the circuit, the diode acts as a closed switch and charges the capacitor to peak input voltage Vm with the polarities.
In all the subsequent positive and negative half cycles, due to large RC time constant, the capacitor does not loose much charge. So Vo almost remains constant.
So for the rest of operation, the equivalent circuit is as shown in figure. The diode is reverse biased in both half cycles, so it remains off.
From figure we can write the expression for Vo as,
This shows that the clamper adds a positive DC shift.
Waveform