Description : In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR
Last Answer : b. CPU
Description : Which operation puts memory address in memory address register and data in DR. a Memory read b. Memory write c Both d. None
Last Answer : b. Memory write
Description : In arithmetic operation numbers of register and the circuits for addition at a. ALU b. MAR c. Both d. None
Last Answer : a. ALU
Description : The register that includes the address of the memory unit is termed asthe _ a. MAR b PC Cc. IR d. None of these
Last Answer : a. MAR
Description : The variable of __ correspond to hardware register: a. RAM b. RIL c. ALU d. MAR
Last Answer : b. RIL
Description : Various machine level components are: a. Address register > Program counter c Data register d. Accumulator register e. Memory of 2K,16 bits/word RAM f. Multiplexers g. Allof these
Last Answer : g. Allof these
Description : Which control transfer passes the function viacontrol_ a Logic b. Operation ce. Circuit d. __ Allof these
Last Answer : ce. Circuit
Description : Which types of jump keeps a 2_byte instruction that holds the range from- 128to127 bytes in the memory location: a. Far jump b. Near jump ce. Short jump d. __ Allof these
Last Answer : ce. Short jump
Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read
Last Answer : d. Address register and read
Description : In register transfer the processor register as. a MAR b PC c IR d RI
Last Answer : d RI
Description : Which are the operation that a computer performs on data that put in register: a. Register transfer b. Arithmetic c. Logical d. Allof these
Last Answer : d. Allof these
Description : Which operation are implemented using a binary counter or combinational circuit: a Register transfer b. Arithmetic c. Logical d. __ Allof these
Last Answer : b. Arithmetic
Description : In stack organization address register is known as the: a. Memory stack b. Stack pointer c. Push operation d. Pop operation
Last Answer : b. Stack pointer
Description : In register stack a stack can be a finite number of a Control word b. Memory word c Transfer word d. — Allof these
Last Answer : b. Memory word
Description : five bits of OPR select one of the operation inthe __ in control register. a. CPU b. RISC ec ALU d. MUX
Last Answer : ec ALU
Description : Which operations are used for addition, subtraction, increment, decrement and complement function: a. Bus b. Memory transfer c. Arithmetic operation d. Allof these
Description : The memory bus is also referred as _ a. Databus b. Address bus c. Memory bus d. — Allof these
Last Answer : a. Databus
Description : The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, ... incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next
Last Answer : c. Instruction register, incremented and next
Description : Outputs of instruction/data path in CU are. a. Reg R/W b. Load/Reg-Reg c. ALU function select d. Load control e. Read control f. IR Latch g. JUMP/Branch/Next PC h_ = All of these
Last Answer : h_ = All of these
Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU
Last Answer : b. Main memory
Description : ___in all digital systems actually performs addition that can handle only two number at a time: a Register b. circuit c digital d. — Allof these
Last Answer : b. circuit
Description : Which language is termed as the symbolic depiction used for indicating the series: a. Random transfer language b. Register transfer language c. Arithmetic transfer language d. __ Allof these
Last Answer : b. Register transfer language
Description : Which micro operations carry information from one register to another. a. Register transfer b. Arithmetic c. Logical d. — Allof these
Last Answer : a. Register transfer
Description : Which language specifies a digital system which uses specified notation: a. Register transfer b. Arithmetic c. Logical d. — Allof these
Description : In every transfer, selection of register by bus is decided by: a. Control signal b No signal c. All signal d. Allof above
Last Answer : a. Control signal
Description : Which is the input of control unit: a. Master clock signal b. Instruction register c. Flags d. Control signals from bus e. Allof these
Last Answer : e. Allof these
Description : The operation is specified by a binary code known as the a. Operand code b. Opcode c. Source code d. — Allof these
Last Answer : b. Opcode
Description : By defining the _ __ register as last in first out stack the sequence can handle nested subroutines: a. S b. J ce. R d. T
Last Answer : ce. R
Description : Copy of instruction in cache memory is known as: a Execution cache b. Data cache c. Instruction cache d. Allof these
Last Answer : c. Instruction cache
Description : __is data paths there is movement of data from one register to another or b/w ALU and a register. a. External b. Boreal c. Internal d. Exchange
Last Answer : c. Internal
Description : Abus organization for seven __ register: a. ALU b. RISC c. CPU d. MUX
Last Answer : c. CPU
Description : Which are contains one or more register that may be referenced by machine instruction: a. Input b. Output c. CPU d. ALU
Description : is just like a circular array: a. Data b. Register c. ALU d. CPU
Last Answer : b. Register
Description : Which are the operation of versatility: a. exchange of information with the outside world via I/O device b. Transfer of data internally with in the central processing unit c. Performs of the basic arithmetic operations d. = Allof these
Last Answer : d. = Allof these
Description : Which are the causes of the interrupt: a. In any single device b. In processor poll devices c. In a device whose ID number is stored on the address bus d. Allof these
Description : Who change the address in the program counter and cause the flow of control to be altered: a Shift manipulation b. Circular manipulation c. Program control instruction d. __ Allof these
Last Answer : c. Program control instruction
Description : ___uses the stack to store return address of subroutine: a. CPU b. Microprocessor c. register d. memory
Last Answer : b. Microprocessor
Description : Addresses in control memory is made by for each register group: a. Address select logic b. Data select logic c. Control select logic d. All of these
Last Answer : a. Address select logic
Description : In post-indexing the contents of the address field are used to access a memory location containing a___ address: Immediate addressing Direct addressing Register addressing ao | None of these
Last Answer : Direct addressing
Description : Which operation are done by increment or decrement the stack pointer: a. Push b. Pop ce. Both d. None
Last Answer : ce. Both
Description : emaphore provides mutual exclusion for accesses to the buffer pool and is initialized to the value: a. Mutex b. Mutual Cc. Memory d. __ Allof these
Last Answer : Mutex
Description : NUMA stands for. a. Number Uniform memory access b. Not Uniform memory access Cc. Non Uniform memory access d. __ Allof these
Last Answer : a. Number Uniform memory access
Description : Which types of register holds a single vector containing at least two read ports and one write ports: a. Data system b. Data base Cc. Memory d. Vector register
Last Answer : d. Vector register
Description : Which is the most important component of a digit computer that interprets the instruction and processes the data contained in computer programs: MU b. ALU c. CPU d. PC
Description : Which part work as a the brain of the computer and performs most of the calculation: a. MU b. PC c. ALU d. CPU
Last Answer : d. CPU
Description : What does MAR stand for? a) Main Address Register b) Memory Access Register c) Main Accessible Register d) Memory Address Register
Last Answer : Answer: d Explanation: MAR is a type of register which is responsible for the fetch operation. MAR is connected to the address bus and it specifies the address for the read and write operations
Description : The decoded instruction is stored in ______ (A) Register (B) Memory Address Register(MAR) (C) Instruction Register(IR) (D) None of the Above
Last Answer : (C) Instruction Register(IR)
Description : Which registers can interact with secondary memory? (A) Register (B) Memory Address Register(MAR) (C) Instruction Register(IR) (D) None of the Above
Last Answer : (B) Memory Address Register(MAR)
Description : Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these
Description : MAR stands for: a. Memory address register b. Memory address recode c. Micro address register d. None of these
Last Answer : a. Memory address register