Which of the following logic operations is performed by the following given combinational circuit ? Image (A) EXCLUSIVE-OR (B) EXCLUSIVE-NOR (C) NAND (D) NOR

Which of the following logic operations is performed by the following given combinational circuit ? 

image

(A) EXCLUSIVE-OR (B) EXCLUSIVE-NOR (C) NAND (D) NOR

by

1 Answer

Answer :

(A) EXCLUSIVE-OR
by

Related questions

What type of logic circuit is indicated by the truth table shown in the illustration? EL-0072 A. OR B. AND C. NOR D. NAND

Description : What type of logic circuit is indicated by the truth table shown in the illustration? EL-0072 A. OR B. AND C. NOR D. NAND

Last Answer : Answer: A

In a logic circuit the NOR and NAND gate functions ____________. A. must be accomplished with a common base transistor arrangement B. are available in diode form C. are exact opposites with the same NOR and NAND inputs D. have output conditions that are exact opposites to the output condition for OR and AND, respectively

Description : In a logic circuit the NOR and NAND gate functions ____________. A. must be accomplished with a common base transistor arrangement B. are available in diode form C. are exact opposites with the ... . have output conditions that are exact opposites to the output condition for OR and AND, respectively

Last Answer : Answer: D

DeMorgan’s first theorem shows the equivalence of (A) OR gate and Exclusive OR gate. (B) NOR gate and Bubbled AND gate. (C) NOR gate and NAND gate. (D) NAND gate and NOT gate

Description : DeMorgan’s first theorem shows the equivalence of (A) OR gate and Exclusive OR gate. (B) NOR gate and Bubbled AND gate. (C) NOR gate and NAND gate. (D) NAND gate and NOT gate

Last Answer : (B) NOR gate and Bubbled AND gate.

Which of the listed logic gates is considered to be a BASIC building block (basic logic gate) used in logic diagrams? A. NAND B. OR C. NOR D. All of the above.

Description : Which of the listed logic gates is considered to be a BASIC building block (basic logic gate) used in logic diagrams? A. NAND B. OR C. NOR D. All of the above.

Last Answer : Answer: B

The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either (A) a NAND or an EX-OR (B) an OR or an EX-NOR (C) an AND or an EX-OR (D) a NOR or an EX-NOR

Description : The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either (A) a NAND or an EX-OR (B) an OR or an EX-NOR (C) an AND or an EX-OR (D) a NOR or an EX-NOR

Last Answer : (D) a NOR or an EX-NOR

Compare combinational logic circuit and sequential logic circuit

Description : Compare combinational logic circuit and sequential logic circuit

Last Answer : Combinational logic Sequential logic The combinational logic circuit consists of logic gate only Sequential logic circuit consists of combinational logic circuit along with memory for storage of ... , multiplexer, demultiplexer etc E.g. counters, shift registers flip-flop etc

What are the operations that can be performed on Files?

Description : What are the operations that can be performed on Files?

Last Answer : Ans: Following operations can be performed on files1. Creation of a file of a specific type. 2. Reading/processing a file. 3. Append/add information to a file. 4. Modify/edit data in a file. 5. Delete items in a file. 6. Update the file.

Which of the following operations can be performed by using FTP. i) Connect to a remote host ii) Select directory iii) Define the transfer mode iv) List file available A) i, and ii only B) i, ii and iii only C) ii, iii and iv only D) All i, ii, iii and iv

Description : Which of the following operations can be performed by using FTP. i) Connect to a remote host ii) Select directory iii) Define the transfer mode iv) List file available A) i, and ii only B) i, ii and iii only C) ii, iii and iv only D) All i, ii, iii and iv

Last Answer : C) ii, iii and iv only

Consider the situation in which assignment operation is very costly. Which of the following sorting algorithm should be performed so that the number of assignment operations is minimized in general? a) Insertion sort b) Selection sort c) Heap sort d) None

Description : Consider the situation in which assignment operation is very costly. Which of the following sorting algorithm should be performed so that the number of assignment operations is minimized in general? a) Insertion sort b) Selection sort c) Heap sort d) None

Last Answer : b) Selection sort

Consider the following operations performed on a stack of size 5: Push(a); Pop(); Push(b); Push(c); Pop(); Push(d); Pop(); Pop(); Push(e); Which of the following statements is correct? (A) Underflow occurs (B) Stack operations are performed smoothly (C) Overflow occurs (D) None of the above

Description : Consider the following operations performed on a stack of size 5: Push(a); Pop(); Push(b); Push(c); Pop(); Push(d); Pop(); Pop(); Push(e); Which of the following statements is correct? (A) Underflow occurs (B) Stack operations are performed smoothly (C) Overflow occurs (D) None of the above

Last Answer : (B) Stack operations are performed smoothly

What will be the output of the following logic diagram? (A) x OR y (B) x AND y (C) x NOR y (D) x XNOR y

Description : What will be the output of the following logic diagram?  (A) x OR y (B) x AND y (C) x NOR y (D) x XNOR y

Last Answer : (C) x NOR y

If the control signals are generated by combinational logic, then they are generated by a type of _______________ controlled unit. a) Micro programmed b) Software c) Logic d) Hardwired

Description : If the control signals are generated by combinational logic, then they are generated by a type of _______________ controlled unit. a) Micro programmed b) Software c) Logic d) Hardwired

Last Answer : Answer: d Explanation: The main task of a control unit is to generate control signals. There are two main types of control units: A hardwired control unit generates control ... combinational logic circuits and the Micro programmed control unit generates control signals by using some softwares

Define combinational logic

Description : Define combinational logic

Last Answer : When logic gates are connected together to produce a specified output for certain specified combinations of input variables, with no storage involved, the resulting circuit is called combinational logic.

Which is the important part of a combinational logic block: a. Index register b. Barrel shifter c. Both a & b d. None of these

Description : Which is the important part of a combinational logic block: a. Index register b. Barrel shifter c. Both a & b d. None of these

Last Answer : b. Barrel shifter

Define combinational logic

Description : Define combinational logic

Last Answer : When logic gates are connected together to produce a specified output for certain specified combinations of input variables, with no storage involved, the resulting circuit is called combinational logic.

Read the following statements: i. Gate is a combinational logic. ii. JK Flip-flop in toggle mode is not

Description : Read the following statements: i. Gate is a combinational logic. ii. JK Flip-flop in toggle mode is not combinational logic. iii. MSJK Flip-flop suffers from race-around. iv. Counters are sequential circuits. Which choice is correct? (A) i, ii (B) i, ii, iv (C) ii, iii, iv (D) i, ii, iii

Last Answer : Read the following statements: i. Gate is a combinational logic. ii. JK Flip-flop in toggle mode is not combinational logic. iii. MSJK Flip-flop suffers from race-around. iv. Counters are sequential circuits. Which choice is ... (A) i, ii (B) i, ii, iv (C) ii, iii, iv (D) i, ii, iii

Which of the following gates can be used to realize all possible combinational logic functions?

Description : Which of the following gates can be used to realize all possible combinational logic functions?  (i) OR gate (ii) NOR gate (iii) Exclusive OR gate (iv) NAND gate (v) AND gate  (A) (iii), (iv) and (v)  (B) (i), (iii) and (iv)  (C) (ii) and (iv)  (D) (i) and (v)

Last Answer : Which of the following gates can be used to realize all possible combinational logic functions?  (i) OR gate (ii) NOR gate (iii) Exclusive OR gate (iv) NAND gate (v) AND gate  (A) (iii), (iv) and (v)  (B) (i), (iii) and (iv)  (C) (ii) and (iv)  (D) (i) and (v)

Actual data processing operations are performed in the arithmetic logic section, but not in the “. Storage section of a processor unit a. Primary b. Accumulator c. Buffer d. Secondary

Description : Actual data processing operations are performed in the arithmetic logic section, but not in the “. Storage section of a processor unit a. Primary b. Accumulator c. Buffer d. Secondary

Last Answer : Primary

Actual data processing operations are performed in the arithmetic logic section, but not in the …. Storage section of a processor unit a. Primary b. Accumulator c. Buffer d. Secondary

Description : Actual data processing operations are performed in the arithmetic logic section, but not in the …. Storage section of a processor unit a. Primary b. Accumulator c. Buffer d. Secondary

Last Answer : a. Primary

Actual data processing operations are performed in the arithmetic logic section, but not in the …. Storage section of a processor unit a. Primary b. Accumulator c. Buffer d. Secondary

Description : Actual data processing operations are performed in the arithmetic logic section, but not in the …. Storage section of a processor unit a. Primary b. Accumulator c. Buffer d. Secondary

Last Answer : a. Primary

If f(x, y) is a digital image, then x, y and amplitude values of f are (A) Finite (B) Infinite (C) Neither finite nor infinite (D) None of the above

Description : If f(x, y) is a digital image, then x, y and amplitude values of f are (A) Finite (B) Infinite (C) Neither finite nor infinite (D) None of the above

Last Answer : (A) Finite

What is the equivalent logic gate of a two-input NAND gate with both inputs inverted?

Description : What is the equivalent logic gate of a two-input NAND gate with both inputs inverted?

Last Answer : OR gate.

A NAND gate has inputs labeled as A, B, and C. If A and B are HIGH, C must be at what logic level to produce a HIGH output?

Description : A NAND gate has inputs labeled as A, B, and C. If A and B are HIGH, C must be at what logic level to produce a HIGH output?

Last Answer : . Low.

A NAND gate has Z and X as inputs. What will be the output logic level if Z is HIGH and X is LOW? A NAND gate has Z and X as inputs. What will be the output logic level if Z is HIGH and X is LOW?

Description : A NAND gate has Z and X as inputs. What will be the output logic level if Z is HIGH and X is LOW?

Last Answer : HIGH.

A universal logic gate is one, which can be used to generate any logic function. Which of the following is a universal logic gate? (A) OR (B) AND (C) XOR (D) NAND

Description : A universal logic gate is one, which can be used to generate any logic function. Which of the following is a universal logic gate? (A) OR (B) AND (C) XOR (D) NAND

Last Answer : Ans: D NAND can generate any logic function.

A NAND gate is called a universal logic element because

Last Answer : A NAND gate is called a universal logic element because any logic function can be realized by NAND gates alone.

Why are NAND and NOR gates called digital building blocks?

Description : Why are NAND and NOR gates called digital building blocks?

Last Answer : NAND and NOR gates are called digital building blocks because they are fundamental building blocks for digital circuits. Both NAND and NOR gates are basic logic gates that can be used to construct ... construct any other logic gates and they can be combined and used to create more complex circuits.

Which one is faster between NAND-SR FF and NOR-SR FF?

Description : Which one is faster between NAND-SR FF and NOR-SR FF?

Last Answer : Ans-well both deals with same principle.but i think NAND-SR FF is faster than NOR-SR FF

i. (X’+Y’) A. Low-pass filter function ii. (X’Y’) B. Sum iii. (XY) C. NAND D. Carry E.NOR a) i-C, ii-E, iii-D b) i-C, ii-E, iii-B c) i-C, ii-B, iii-D d) i-C, ii-E, iii-A

Description : i. (X’+Y’) A. Low-pass filter function ii. (X’Y’) B. Sum iii. (XY) C. NAND D. Carry E.NOR a) i-C, ii-E, iii-D b) i-C, ii-E, iii-B c) i-C, ii-B, iii-D d) i-C, ii-E, iii-A

Last Answer : Ans: i-C, ii-E, iii-D

Using DeMorgan's Theorem we can convert any AND-OR structure into a. NAND-NAND b. OR-NAND c. NAND-NOR d. NOR-NAND

Description : Using DeMorgan's Theorem we can convert any AND-OR structure into a. NAND-NAND b. OR-NAND c. NAND-NOR d. NOR-NAND

Last Answer : a. NAND-NAND

Which of following are known as universal gates (A) NAND & NOR. (B) AND & OR. (C) XOR & OR. (D) None.

Description : Which of following are known as universal gates (A) NAND & NOR. (B) AND & OR. (C) XOR & OR. (D) None.

Last Answer : Ans: A NAND & NOR are known as universal gates, because any digital circuit can be realized completely by using either of these two gates.

The gates required to build a half adder are (A) EX-OR gate and NOR gate (B) EX-OR gate and OR gate (C) EX-OR gate and AND gate (D) Four NAND gates.

Description : The gates required to build a half adder are (A) EX-OR gate and NOR gate (B) EX-OR gate and OR gate (C) EX-OR gate and AND gate (D) Four NAND gates.

Last Answer : (C) EX-OR gate and AND gate

Why NAND and NOR gate are called as universal gate? Draw AND gate using NAND gate only.

Description : Why NAND and NOR gate are called as universal gate? Draw AND gate using NAND gate only. 

Last Answer : Universal gate - All basic gates functionality can be implemented using NAND and NOR gate hence these gates are called as universal gates.  AND gate using NAND gate

Sketch symbol of NAND gate and NOR gate.

Description : Sketch symbol of NAND gate and NOR gate.

Last Answer : Symbol of NAND gate and NOR gate

Which operation are implemented using a binary counter or combinational circuit: a Register transfer b. Arithmetic c. Logical d. __ Allof these

Description : Which operation are implemented using a binary counter or combinational circuit: a Register transfer b. Arithmetic c. Logical d. __ Allof these

Last Answer : b. Arithmetic

Which control unit is implemented as combinational circuit in the hardware. a. Microprogrammed control unit b. Hardwired control unit c Blockprogrammed control unit d. Macroprogrammed control unit

Description : Which control unit is implemented as combinational circuit in the hardware. a. Microprogrammed control unit b. Hardwired control unit c Blockprogrammed control unit d. Macroprogrammed control unit

Last Answer : b. Hardwired control unit

What is a sequential circuit and What is a combinational circuit?Is there any difference between them? If yes what is it?

Description : What is a sequential circuit and What is a combinational circuit?Is there any difference between them? If yes what is it?

Last Answer : Ans-Combinational circuit are those whose output depends only upon the present inputs but in sequential circuit the output depends upon both present and past inputs. that is the difference.

What is a sequential circuit and What is a combinational circuit? Is there any difference between them? If yes what is it?

Description : What is a sequential circuit and What is a combinational circuit? Is there any difference between them? If yes what is it?

Last Answer : Ans-Combinational circuit are those whose output depends only upon the present inputs but in sequential circuit the output depends upon both present and past inputs. that is the difference Combinational ... the feedback path. Ex of SEQ Circuit: Encoder Decoder etc Ex of Comb Circuit; Flipflop

A full adder is a combinational circuit that performs the arithmetic sum of three input bits and produces a

Description : A full adder is a combinational circuit that performs the arithmetic sum of three input bits and produces a (a) sum output (b) sum output and a carry (c) sum output with two carries (d) two sums with two carries

Last Answer : A full adder us an a combination logical circuit which will produces an sum and carry when ever more than two inputs were given.

................ allows individual row operation to be performed on a given result set or on the generated by a selected by a selected statement. A) Procedure B) Trigger C) Curser D) None of above

Description : ................ allows individual row operation to be performed on a given result set or on the generated by a selected by a selected statement. A) Procedure B) Trigger C) Curser D) None of above

Last Answer : C) Curser

Which of the following statements is false? (A) Optimal binary search tree construction can be performed efficiently using dynamic programming. (B) Breadth-first search cannot be used to find connected components of a graph. (C) Given the prefix and postfix walks of a binary tree, the tree cannot be reconstructed uniquely. (D) Depth-first-search can be used to find the components of a graph. (1) A (2) B (3) C (4) D

Description : Which of the following statements is false? (A) Optimal binary search tree construction can be performed efficiently using dynamic programming. (B) Breadth-first search cannot be used to find connected components of a graph. (C) ... used to find the components of a graph. (1) A (2) B (3) C (4) D 

Last Answer : Answer: 2

What are the final values of Q1 and Q0 after 4 clock cycles, if initial values are 00 in the sequential circuit shown below: Image (A) 11 (B) 10 (C) 01 (D) 00

Description : What are the final values of Q1 and Q0 after 4 clock cycles, if initial values are 00 in the sequential circuit shown below: (A) 11 (B) 10 (C) 01 (D) 00

Last Answer : (D) 00

In Propositional Logic, given P and P→Q, we can infer ........... (A) ~Q (B) Q (C) P∧Q (D) ~P∧Q

Description : In Propositional Logic, given P and P→Q, we can infer ........... (A) ~Q (B) Q (C) P∧Q (D) ~P∧Q 

Last Answer : (B) Q 

The output of an exclusive–NOR gate is 1. Which input combination is correct?

Description : The output of an exclusive–NOR gate is 1. Which input combination is correct? (1) A = 1, B = 0 (2) A = 0, B = 1 (3) A = 0, B = 0 (4) None of these 

Last Answer : The output of an exclusive–NOR gate is 1. Which input combination is correct? (1) A = 1, B = 0 (2) A = 0, B = 1 (3) A = 0, B = 0 (4) None of these 

The number of distinct binary images which can be generated from a given binary image of right M × N are (A) M + N (B) M × N (C) 2M + N (D) 2MN

Description : The number of distinct binary images which can be generated from a given binary image of right M × N are (A) M + N (B) M × N (C) 2M + N (D) 2MN

Last Answer : (D) 2MN

Given a Non-deterministic Finite Automation (NFA) with states p and r as initial and final states respectively transition table as given below Image The minimum number of states required in Deterministic Finite Automation (DFA) equivalent to NFA is (A) 5 (B) 4 (C) 3 (D) 2

Description : Given a Non-deterministic Finite Automation (NFA) with states p and r as initial and final states respectively transition table as given below  The minimum number of states required in Deterministic Finite Automation (DFA) equivalent to NFA is (A) 5 (B) 4 (C) 3 (D) 2

Last Answer : (C) 3 

The transformation matrix required for conversion of CMY colour model to RGB colour model is given as Image

Description : The transformation matrix required for conversion of CMY colour model to RGB colour model is given as

Last Answer : Answer: C

Given the following statements : S1 : The subgraph-isomorphism problem takes two graphs G1 and G2 and asks whether G1 is a subgraph of G2. S2 : The set-partition problem takes as input a set S of numbers and asks whether the numbers can be partitioned into two sets A Image Which of the following is true ? (A) S1 is NP problem and S2 is P problem. (B) S1 is NP problem and S2 is NP problem. (C) S1 is P problem and S2 is P problem. (D) S1 is P problem and S2 is NP problem.

Description : Given the following statements :  S1 : The subgraph-isomorphism problem takes two graphs G1 and G2 and asks whether G1 is a subgraph of G2.  S2 : The set-partition problem takes as input a set S of numbers and ... S1 is P problem and S2 is P problem. (D) S1 is P problem and S2 is NP problem.

Last Answer : (B) S1 is NP problem and S2 is NP problem.