Description : is the first step in the evolution of programming languages. a. machine language b. assembly language c. code language d. none of these
Last Answer : b. assembly language
Description : The control unit and arithmetic logic unit are know as the __ a. Central program unit b. Central processing unit
Last Answer : b. Central processing unit
Description : Which microprocessor has the control unit, memory unit and arithmetic and logic unit: a. Pentium IV processor b Pentium V processor c. Pentium III processor d. None of these
Last Answer : a. Pentium IV processor
Description : In register transfer which system is a sequential logic system in which flip-flops and gates are constructed: a. Digital system b. Register Cc. Data d. None
Last Answer : a. Digital system
Description : Which control transfer passes the function viacontrol_ a Logic b. Operation ce. Circuit d. __ Allof these
Last Answer : ce. Circuit
Description : In 3 state gate two states act as signals equal to. a. Logic O b. Logic 1 c. None of these d. Botha&b
Last Answer : d. Botha&b
Description : Addresses in control memory is made by for each register group: a. Address select logic b. Data select logic c. Control select logic d. All of these
Last Answer : a. Address select logic
Description : Branch logic determines which should be adopted to select the next_ value among possibilities. a. CAR b. GAR c. HAR d. TAR
Last Answer : a. CAR
Description : Rules of FSM are encoded in. a. ROM b. Random logic c. Programmable logic array d. Allof these
Last Answer : d. Allof these
Description : Full form of PLA in CU: a. Progrmmable Logic Array b. Programs Load Array c. Programmable Logic Accumulator d. all of these
Last Answer : a. Progrmmable Logic Array
Description : Abbreviation ASCII stands for: a. American standard code for information interchange b. Abbreviation standard code for information interchange c. Both d. None of these
Last Answer : a. American standard code for information interchange
Description : IR stands for. a. Input representation b. Intermediate representation c. Both d. None
Last Answer : b. Intermediate representation
Description : IDE stands for: a. Input device electronics b. Integrated device electronic c. Both d. None
Last Answer : b. Integrated device electronic
Description : ATA stands for. a. Advance technology attachment b. Advance teach attachment c. Both d. None
Last Answer : a. Advance technology attachment
Description : SDRAM stands for. a. System dynamic random access memory b. Synchronous dynamic random access memory c. Both d. None
Last Answer : b. Synchronous dynamic random access memory
Description : SPARC stands for. a. Scalable programmer architecture b. Scalable processor architecture c Scalable point architecture d. None of these
Last Answer : b. Scalable processor architecture
Description : Markers in subroutine cannot be accepted as limits whereas this markers stands for: a. Top of stack b. Bottom of stack c. Middle of stack d. Allof these
Last Answer : a. Top of stack
Description : RPN stands for. a. _ Reverse polish notation b. Read polish notation c. Random polish notation d. None of these
Last Answer : a. _ Reverse polish notation
Description : EA stands for. a. Effective add b. Effective absolute c. Effective address d. End address
Last Answer : c. Effective address
Description : SMP Stands for: a. System multiprocessor b. Symmetric multiprocessor c. Both d. None
Last Answer : b. Symmetric multiprocessor
Description : NUMA stands for. a. Number Uniform memory access b. Not Uniform memory access Cc. Non Uniform memory access d. __ Allof these
Last Answer : a. Number Uniform memory access
Description : SIMD stands for: a. System instruction multiple data b. Single instruction multiple data c. Symmetric instruction multiple data d. Scale instruction multiple data
Last Answer : b. Single instruction multiple data
Description : MIMD stands for: a. Multiple input multiple data b. Memory input multiple data c. Multiple instruction multiple data d. Memory instruction multiple data
Last Answer : c. Multiple instruction multiple data
Description : High level language C supports register transfer technique for _ application. a. Executing b. Compiling c. Both d. None
Last Answer : a. Executing
Description : __are used to translate high level language instructions to a machine code. a. Translators b. Interpreters c. Compilers d. None of these
Last Answer : c. Compilers
Description : Before checking the program for errors in translating code into machine language the high level language code is loaded into __ a. Register b. Memory c. Data d. CPU
Last Answer : b. Memory
Description : Which language processor converts an HLL program into machine language at once? -Technology
Last Answer : Compiler is a language processor which converts whole HLL program into machine language at once which can be understood by the processor.
Description : What is the full form of 'HLL' ? -How To ?
Last Answer : The full form of 'HLL' is Hindustan Lever Limited
Description : The database schema is written in (A) HLL (B) DML (C) DDL (D) DCL
Last Answer : (C) DDL
Description : It contains the stack for PC storage during subroutine calls and input/output interrupt services: a. Seven- level hardware b. Eight- level hardware
Last Answer : b. Eight- level hardware
Description : Various machine level components are: a. Address register > Program counter c Data register d. Accumulator register e. Memory of 2K,16 bits/word RAM f. Multiplexers g. Allof these
Last Answer : g. Allof these
Description : every bit of register has. a 2 common line b 3 common line c. 1 common line d none of these
Last Answer : c. 1 common line
Description : To invoke assembler following command are given at command line: a. $ hello.s -o hello.o b. — $as hello.s -o 0 c. $ as hello —-o hello.o d. $ashello.s—o hello.o
Last Answer : d. $ashello.s—o hello.o
Description : Parameters can be stacked by just as with procedures: a. Asterisk(*) b. Arrow c. Line d. ‘Pipeline
Last Answer : a. Asterisk(*)
Description : function select takes op code in IR translating to function of ALU and it may be compact binary code or one line per ALU: a ALU b CPU c. Memory d. Cache
Last Answer : a ALU
Description : In 3 state gate third position termed as high impedance state which acts as. a. Open circuit b. — Close circuit c. None of these d. All of above
Last Answer : a. Open circuit
Description : In the third generation of computers: a. Distributed data processing first became popular b. An operating system was first developed c. High-level prcedu7ral languages were firs used d. On-line, real time systems first became popular
Last Answer : On-line, real time systems first became popular
Last Answer : d. On-line, real time systems first became popular
Description : The statement comprising the limitations of FOL is/are ____________ a) Expressiveness b) Formalizing Natural Languages c) Many-sorted Logic d) All of the mentioned
Last Answer : d) All of the mentioned
Description : emaphore provides mutual exclusion for accesses to the buffer pool and is initialized to the value: a. Mutex b. Mutual Cc. Memory d. __ Allof these
Last Answer : Mutex
Description : Which section is basically a sequence of instruction with a clear indication of beginning and end for updating shared variables. a. Racing section b. Critical section c. d. Both None of thes
Last Answer : . Critical sectio
Description : In which section only one process is allowed to access the shared variable and all other have to wait. a. Critical section b. Racing section Cc. Entry section d. Remainder section
Last Answer : . Critical section
Description : hich section is the remaining part of a process’s code: a. Racing section b. Critical section Cc. Entry section d. Reminder secti
Last Answer : b. Entry section
Description : Which are the characteristics of deadlocks. a. Mutual exclusion b. Hold and wait Cc. No pre-emption d. = Circular wait e. Allof these
Last Answer : e. Allof these
Description : How many events concerning RAG can occur in a system: a. 1 b 2 c. 3 d 4
Last Answer : c. 3
Description : Which are the events concerning RAG can occur in a system: a. Request for a resource b. Allocation of a resource c. Release of resource d. Allof these
Description : How many methods for handling deadlocks: a. 1 b 2 c. 3 d 4
Description : Which are the method for handling deadlocks. a. Deadlock prevention b. Deadlock avoidance c. Deadlock detection d. Allof these
Description : How many condition that should be met in order to produce a deadlock. a. 2 b 4 Cc. 6 d 8
Last Answer : b 4
Description : Which are the condition that should be met in order to produce a deadlock. a. Mutual exclusion b. Hold and Wait Cc. No preemption d. Circular wait e. Allofthese
Last Answer : e. Allofthese