SIMD stands for: a. System instruction multiple data b. Single instruction multiple data c. Symmetric instruction multiple data d. Scale instruction multiple data

SIMD stands for:
a. System instruction multiple data
b. Single instruction multiple data
c. Symmetric instruction multiple data
d. Scale instruction multiple data
by

1 Answer

Answer :

b. Single instruction multiple data
by

Related questions

Which processor has a single instruction multiple data stream organization that manipulates the common instruction by means of multiple functional units. a. Attached array processor b. SIMD array processor c. Both d. None

Description : Which processor has a single instruction multiple data stream organization that manipulates the common instruction by means of multiple functional units. a. Attached array processor b. SIMD array processor c. Both d. None

Last Answer : b. SIMD array processor

MIMD stands for: a. Multiple input multiple data b. Memory input multiple data c. Multiple instruction multiple data d. Memory instruction multiple data

Description : MIMD stands for: a. Multiple input multiple data b. Memory input multiple data c. Multiple instruction multiple data d. Memory instruction multiple data

Last Answer : c. Multiple instruction multiple data

Von Neumann Architecture is a _______ A. Multiple Instruction Multiple Data(MIMD) B. Single Instruction Multiple Data(SIMD) C. Multiple Instruction Single Data(MISD) D. Single Instruction Single Data(SISD)

Description : Von Neumann Architecture is a _______ A. Multiple Instruction Multiple Data(MIMD) B. Single Instruction Multiple Data(SIMD) C. Multiple Instruction Single Data(MISD) D. Single Instruction Single Data(SISD)

Last Answer : D. Single Instruction Single Data(SISD)

How many ALU(s) is/are control by one control unit is SIMD (single instruction stream, multiple data stream) architecture? a) one or more ALUs b) One ALU c) Only two ALU d) Impossible to say

Description : How many ALU(s) is/are control by one control unit is SIMD (single instruction stream, multiple data stream) architecture? a) one or more ALUs b) One ALU c) Only two ALU d) Impossible to say

Last Answer : a) one or more ALUs

SMP Stands for: a. System multiprocessor b. Symmetric multiprocessor c. Both d. None

Description : SMP Stands for: a. System multiprocessor b. Symmetric multiprocessor c. Both d. None

Last Answer : b. Symmetric multiprocessor

Which are the types of array processor: a. Attached array processor b. SIMD array processor c. Both d. None

Description : Which are the types of array processor: a. Attached array processor b. SIMD array processor c. Both d. None

Last Answer : c. Both

In data transfer manipulation designing as instruction set for a system isa complex_ a. Art b. System Cc. Computer d. None of these

Description : In data transfer manipulation designing as instruction set for a system isa complex_ a. Art b. System Cc. Computer d. None of these

Last Answer : a. Art

The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read

Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read

Last Answer : d. Address register and read

The contents of the program counter isthe __——__—oof the instruction to be run. a. Data b. Address c. Counter d. None of these

Description : The contents of the program counter isthe __——__—oof the instruction to be run. a. Data b. Address c. Counter d. None of these

Last Answer : b. Address

Which is the most important component of a digit computer that interprets the instruction and processes the data contained in computer programs: MU b. ALU c. CPU d. PC

Description : Which is the most important component of a digit computer that interprets the instruction and processes the data contained in computer programs: MU b. ALU c. CPU d. PC

Last Answer : c. CPU

Copy of instruction in cache memory is known as: a Execution cache b. Data cache c. Instruction cache d. Allof these

Description : Copy of instruction in cache memory is known as: a Execution cache b. Data cache c. Instruction cache d. Allof these

Last Answer : c. Instruction cache

Outputs of instruction/data path in CU are. a. Reg R/W b. Load/Reg-Reg c. ALU function select d. Load control e. Read control f. IR Latch g. JUMP/Branch/Next PC h_ = All of these

Description : Outputs of instruction/data path in CU are. a. Reg R/W b. Load/Reg-Reg c. ALU function select d. Load control e. Read control f. IR Latch g. JUMP/Branch/Next PC h_ = All of these

Last Answer : h_ = All of these

Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU

Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU

Last Answer : b. Main memory

The length of instruction set depends on: a. Data size b. Memory size c. Both d. None

Description : The length of instruction set depends on: a. Data size b. Memory size c. Both d. None

Last Answer : b. Memory size

Which is data manipulation types are. a. Arithmetic instruction b. Shift instruction c. Logical and bit manipulation instructions d. All of these

Description : Which is data manipulation types are. a. Arithmetic instruction b. Shift instruction c. Logical and bit manipulation instructions d. All of these

Last Answer : d. All of these

Arithmetic instruction are used to perform operation on: a. Numerical data b. Non-numerical data c. Both d. None

Description : Arithmetic instruction are used to perform operation on: a. Numerical data b. Non-numerical data c. Both d. None

Last Answer : a. Numerical data

In which instruction are used to perform Boolean operation on non-numerical data: a. Logical and bit manipulation b. Shift manipulation c. Circular manipulation d. None of these

Description : In which instruction are used to perform Boolean operation on non-numerical data: a. Logical and bit manipulation b. Shift manipulation c. Circular manipulation d. None of these

Last Answer : a. Logical and bit manipulation

Which section is basically a sequence of instruction with a clear indication of beginning and end for updating shared variables. a. Racing section b. Critical section c. d. Both None of thes

Description : Which section is basically a sequence of instruction with a clear indication of beginning and end for updating shared variables. a. Racing section b. Critical section c. d. Both None of thes

Last Answer : . Critical sectio

Two important fields of an instruction are. a. Opcode b. Operand c. Only a d. Botha&b

Description : Two important fields of an instruction are. a. Opcode b. Operand c. Only a d. Botha&b

Last Answer : d. Botha&b

The complete set of op-codes for a particular microprocessor defines the_ set for that processor: a. Code b. Function c. Module d. Instruction

Description : The complete set of op-codes for a particular microprocessor defines the_ set for that processor: a. Code b. Function c. Module d. Instruction

Last Answer : d. Instruction

Which is the method by which instructions are selected for execution: a. Instruction selection b. — Selection control c. Instraction sequencing d. All of these

Description : Which is the method by which instructions are selected for execution: a. Instruction selection b. — Selection control c. Instraction sequencing d. All of these

Last Answer : c. Instraction sequencing

The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these

Description : The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these

Last Answer : a. The address of next instruction to be run

As the instruction length increases ————_ of instruction addresses in all the instruction is_ a. Implicit inclusion b. Implicit and disadvantageous c. Explicit and disadvantageous d. Explicit and disadvantageous

Description : As the instruction length increases ————_ of instruction addresses in all the instruction is_ a. Implicit inclusion b. Implicit and disadvantageous c. Explicit and disadvantageous d. Explicit and disadvantageous

Last Answer : c. Explicit and disadvantageous

__is the sequence of operations performed by CPU in processing an instruction: a. Execute cycle b. Fetch cycle c. Decode d. Instruction cycle

Description : __is the sequence of operations performed by CPU in processing an instruction: a. Execute cycle b. Fetch cycle c. Decode d. Instruction cycle

Last Answer : d. Instruction cycle

The time required to complete one instruction is called. a. Fetch time b. Execution time c. Control time d. All of these

Description : The time required to complete one instruction is called. a. Fetch time b. Execution time c. Control time d. All of these

Last Answer : b. Execution time

_is the step during which a new instruction is read from the memory: a Decode b. Fetch c. Execute d. None of these

Description : _is the step during which a new instruction is read from the memory: a Decode b. Fetch c. Execute d. None of these

Last Answer : b. Fetch

is the step during which the operations specified by the instruction are executed: a. Execute b. Decode c. Both a& b d. None of these

Description : is the step during which the operations specified by the instruction are executed: a. Execute b. Decode c. Both a& b d. None of these

Last Answer : a. Execute

Decode is the step during which instruction is__ a. Initialized b. Incremented c. Decoded d. Bothb&c

Description : Decode is the step during which instruction is__ a. Initialized b. Incremented c. Decoded d. Bothb&c

Last Answer : c. Decoded

The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, incremented and next b. Instruction register, incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next

Description : The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, ... incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next

Last Answer : c. Instruction register, incremented and next

Execution of instruction specified by instruction to perform: a. Operation b. Operands c. Both a &b d. None of these

Description : Execution of instruction specified by instruction to perform: a. Operation b. Operands c. Both a &b d. None of these

Last Answer : a. Operation

Which are designed to interpret a specified number of instruction code. a. Programmer b. Processors c. Instruction d. Opcode

Description : Which are designed to interpret a specified number of instruction code. a. Programmer b. Processors c. Instruction d. Opcode

Last Answer : b. Processors

__is divided into a number of fields and is represented as a sequence of bits: a. instruction b. — instruction set c. instruction code d. parity code

Description : __is divided into a number of fields and is represented as a sequence of bits: a. instruction b. — instruction set c. instruction code d. parity code

Last Answer : a. instruction

Which unit is necessary for the execution of instruction: a. Timing b. Control ce. Both d. None of these

Description : Which unit is necessary for the execution of instruction: a. Timing b. Control ce. Both d. None of these

Last Answer : ce. Both

sis given an instruction in machine language this instruction is fetched from the memory by the CPU to execute: a. ALU b. CPU c. MU d. All of these

Description : sis given an instruction in machine language this instruction is fetched from the memory by the CPU to execute: a. ALU b. CPU c. MU d. All of these

Last Answer : b. CPU

Which cycle refers to the time period during which one instruction is fetched and executed by the CPU: a. Fetch cycle b. Instruction cycle c. Decode cycle d. Execute cycle

Description : Which cycle refers to the time period during which one instruction is fetched and executed by the CPU: a. Fetch cycle b. Instruction cycle c. Decode cycle d. Execute cycle

Last Answer : b. Instruction cycle

Which instruction are 32 bits long , with extra 16 bits. a. Memory reference instruction b. Memory reference format c. Both d. None of these

Description : Which instruction are 32 bits long , with extra 16 bits. a. Memory reference instruction b. Memory reference format c. Both d. None of these

Last Answer : a. Memory reference instruction

Which are instruction in which two machine cycle are required: a. Instruction cycle b. Memory reference instruction c. Both d. None of these

Description : Which are instruction in which two machine cycle are required: a. Instruction cycle b. Memory reference instruction c. Both d. None of these

Last Answer : b. Memory reference instruction

Which instruction are used in multithreaded parallel processor architecture. a. Memory reference instruction b. Memory reference format c. Both d. None of these

Description : Which instruction are used in multithreaded parallel processor architecture. a. Memory reference instruction b. Memory reference format c. Both d. None of these

Last Answer : a. Memory reference instruction

Which instruction are arranged as per the protocols of memory reference format of the input file in a simple ASCII sequence of integers between the range O to 99 separated by spaces without formatted text and symbols: a. Memory reference instruction b. Memory reference format c. Both d. None of these

Description : Which instruction are arranged as per the protocols of memory reference format of the input file in a simple ASCII sequence of integers between the range O to 99 separated by spaces without formatted text ... : a. Memory reference instruction b. Memory reference format c. Both d. None of these

Last Answer : a. Memory reference instruction

is an external hardware event which causes the CPU to interrupt the current instruction sequence: a. Input interrupt b. Output interrupt c. Both d. None of these

Description : is an external hardware event which causes the CPU to interrupt the current instruction sequence: a. Input interrupt b. Output interrupt c. Both d. None of these

Last Answer : c. Both

Which register holds the next instruction to be executed:

Description : Which register holds the next instruction to be executed:

Last Answer : c. Program control register

Which register holds the current instruction to be executed. a. Instruction register b. Program register 9 Control register a None of these

Description : Which register holds the current instruction to be executed. a. Instruction register b. Program register 9 Control register a None of these

Last Answer : a. Instruction register

Each instruction is also accompanied by a___ : a. Microprocessor b. Microcode c. Both d. None of these

Description : Each instruction is also accompanied by a___ : a. Microprocessor b. Microcode c. Both d. None of these

Last Answer : b. Microcode

In second pass, assembler creates _ in binary format for every instruction in program and then refers to the symbol table to giving every symbol an_ _ relating the segment. a. Code and program b. Program and instruction c. Code and offset d. All of these

Description : In second pass, assembler creates _ in binary format for every instruction in program and then refers to the symbol table to giving every symbol an_ _ relating the segment. a. Code and program b. Program and instruction c. Code and offset d. All of these

Last Answer : c. Code and offset

Modern assemblers for RISC based architectures make optimization of instruction scheduling to make use of CPU __ efficiently: a. Pipeline b. Without pipeline c. Botha &b d. None of these

Description : Modern assemblers for RISC based architectures make optimization of instruction scheduling to make use of CPU __ efficiently: a. Pipeline b. Without pipeline c. Botha &b d. None of these

Last Answer : a. Pipeline

To design a program it requires __ os a. Program specification b. Code specification c. Instruction specification d. Problem specification

Description : To design a program it requires __ os a. Program specification b. Code specification c. Instruction specification d. Problem specification

Last Answer : a. Program specification

Call instruction is written inthe ss program. a. Main b. Procedures c. Program d. Memory

Description : Call instruction is written inthe ss program. a. Main b. Procedures c. Program d. Memory

Last Answer : a. Main

Return instruction is written in_ to written to main program: a. Subroutine b. Main program c. Botha &b d. None of these

Description : Return instruction is written in_ to written to main program: a. Subroutine b. Main program c. Botha &b d. None of these

Last Answer : a. Subroutine

When subroutine is called contents of program counter is location address of __ instruction following call instruction is stored on _ __and program execution is transferred to __ address. a. Non executable, pointer and subroutine b. Executable, Stack and Main program Cc. Executable, Queue and Subroutine d. Executable, Stack and Subroutine

Description : When subroutine is called contents of program counter is location address of __ instruction following call instruction is stored on _ __and program execution is transferred to __ address. a. Non ... , Stack and Main program Cc. Executable, Queue and Subroutine d. Executable, Stack and Subroutine

Last Answer : d. Executable, Stack and Subroutine

Each instruction is executed by set of micro operations termed as. a. Micro instructions b. Mini instructions c. Botha &b d. None of these

Description : Each instruction is executed by set of micro operations termed as. a. Micro instructions b. Mini instructions c. Botha &b d. None of these

Last Answer : a. Micro instructions