Description : NUMA stands for. a. Number Uniform memory access b. Not Uniform memory access Cc. Non Uniform memory access d. __ Allof these
Last Answer : a. Number Uniform memory access
Description : RPN stands for. a. _ Reverse polish notation b. Read polish notation c. Random polish notation d. None of these
Last Answer : a. _ Reverse polish notation
Description : A computer having writable control memory is known as_ a. Static micro programmable b. Dynamic micro programmable c. Botha & b d. None of these
Last Answer : b. Dynamic micro programmable
Description : During program execution content of main memory undergo changes and, but control memory has _ microprogram: a. Static b. Dynamic c. Compile time d. Fixed
Last Answer : d. Fixed
Description : DMA stands for: a. Dynamic memory access b. Data memory access c. Direct memory access d. Both B and C
Last Answer : d. Both B and C
Description : Which of the following is used for very high speed searching applications ? (1) Flash Memory (2) Content-addressable Memory (3) Dynamic Random Access Memory (4) Static Random Access Memory
Last Answer : Content-addressable Memory
Description : MIMD stands for: a. Multiple input multiple data b. Memory input multiple data c. Multiple instruction multiple data d. Memory instruction multiple data
Last Answer : c. Multiple instruction multiple data
Description : What are 2 advantages of cache memory: a. Reduction of average access time for CPU memory b. Reduction of bandwidth of available memory of CPU c. Botha&b d. None of these
Last Answer : c. Botha&b
Description : In post-indexing the contents of the address field are used to access a memory location containing a___ address: Immediate addressing Direct addressing Register addressing ao | None of these
Last Answer : Direct addressing
Description : _______is not as fast as SRAM but is cheaper and is used for main memory. Each bit uses a single capacitor and single transistor circuit.: a) DRAM b) SDRAM c) Both of Above d) None of These
Last Answer : a) DRAM
Description : RAM stands for: a) Read Access Memory b) Random Access Memory c) Rewritable Access Memory d) None of These
Last Answer : b) Random Access Memory
Description : SMP Stands for: a. System multiprocessor b. Symmetric multiprocessor c. Both d. None
Last Answer : b. Symmetric multiprocessor
Description : Abbreviation ASCII stands for: a. American standard code for information interchange b. Abbreviation standard code for information interchange c. Both d. None of these
Last Answer : a. American standard code for information interchange
Description : IR stands for. a. Input representation b. Intermediate representation c. Both d. None
Last Answer : b. Intermediate representation
Description : IDE stands for: a. Input device electronics b. Integrated device electronic c. Both d. None
Last Answer : b. Integrated device electronic
Description : ATA stands for. a. Advance technology attachment b. Advance teach attachment c. Both d. None
Last Answer : a. Advance technology attachment
Description : ______ is the fastest form of RAM but also the most expensive. Due to its cost it is not used as main memory but rather for cache memory: a) SRAM b) DRAM c) SDRAM d) None of These
Last Answer : a) SRAM
Description : Which language is termed as the symbolic depiction used for indicating the series: a. Random transfer language b. Register transfer language c. Arithmetic transfer language d. __ Allof these
Last Answer : b. Register transfer language
Description : The method of writing symbol to indicate a provided computational process is called as a: a. Programming language b. Random transfer language c. Register transfer language d. Arithmetic transfer language
Last Answer : a. Programming language
Description : Rules of FSM are encoded in. a. ROM b. Random logic c. Programmable logic array d. Allof these
Last Answer : d. Allof these
Description : _________is a copy of Basic Input/Output Operating System (BIOS) routines from Read Only Memory (ROM) into a special area of RAM so that they can be accessed more quickly. A. Dynamic RAM B. Shadow RAM C. Synchronous Graphics RAM D. Video RAM
Last Answer : B. Shadow RAM
Description : SIMD stands for: a. System instruction multiple data b. Single instruction multiple data c. Symmetric instruction multiple data d. Scale instruction multiple data
Last Answer : b. Single instruction multiple data
Description : SPARC stands for. a. Scalable programmer architecture b. Scalable processor architecture c Scalable point architecture d. None of these
Last Answer : b. Scalable processor architecture
Description : Markers in subroutine cannot be accepted as limits whereas this markers stands for: a. Top of stack b. Bottom of stack c. Middle of stack d. Allof these
Last Answer : a. Top of stack
Description : EA stands for. a. Effective add b. Effective absolute c. Effective address d. End address
Last Answer : c. Effective address
Description : HLL stands for: a. High level languages b. High level line c. High level logic d. High level limit
Last Answer : a. High level languages
Description : The source/destination of operands can be the_ or one of the general-purpose register: a. Memory b. One c. both d. None of these
Last Answer : a. Memory
Description : Which instruction are 32 bits long , with extra 16 bits. a. Memory reference instruction b. Memory reference format c. Both d. None of these
Last Answer : a. Memory reference instruction
Description : Which is addressed by sign extending the 16-bit displacement to 32-bit: a. Memory address b. Effective memory address c. Both a and b d. None of these
Last Answer : b. Effective memory address
Description : Which are instruction in which two machine cycle are required: a. Instruction cycle b. Memory reference instruction c. Both d. None of these
Last Answer : b. Memory reference instruction
Description : Which instruction are used in multithreaded parallel processor architecture. a. Memory reference instruction b. Memory reference format c. Both d. None of these
Description : Which instruction are arranged as per the protocols of memory reference format of the input file in a simple ASCII sequence of integers between the range O to 99 separated by spaces without formatted text ... : a. Memory reference instruction b. Memory reference format c. Both d. None of these
Description : of the primary memory of the computer is limited. a. Storage capacity b. Magnetic disk c. Both d. None of these
Last Answer : a. Storage capacity
Description : Which operation puts memory address in memory address register and data in DR. a Memory read b. Memory write c Both d. None
Last Answer : b. Memory write
Description : Memory —mapped ___is used this is just another memory address. a. Input b. Output c. Both d. None
Last Answer : c. Both
Description : The length of instruction set depends on: a. Data size b. Memory size c. Both d. None
Last Answer : b. Memory size
Description : In which section only one process is allowed to access the shared variable and all other have to wait. a. Critical section b. Racing section Cc. Entry section d. Remainder section
Last Answer : . Critical section
Description : In RISC architecture access to registers is made as a block and register file in a particular register can be selected by using: a. Multiplexer b. Decoder c. Subtractor d. Adder
Last Answer : b. Decoder
Description : On what method search in cache memory used by the system. a. Cache directing b. Cache mapping c. Cache controlling d. Cache invalidation
Last Answer : b. Cache mapping
Description : Which types of register holds a single vector containing at least two read ports and one write ports: a. Data system b. Data base Cc. Memory d. Vector register
Last Answer : d. Vector register
Description : Parallel computing means doing several takes simultaneously thus improving the performance of the a. Data system b. Computer system Cc. Memory d. Vector register
Last Answer : b. Computer system
Description : emaphore provides mutual exclusion for accesses to the buffer pool and is initialized to the value: a. Mutex b. Mutual Cc. Memory d. __ Allof these
Last Answer : Mutex
Description : Which memory is assembled between main memory and CPU: a. Primary memory b. Cache memory Cc. Botha & b d. None of these
Last Answer : b. Cache memory
Description : specify where to get the source and destination operands for the operation specified by the a. Operand fields and opcode b. Opcode and operand c. Source and destination d. Cpu and memory
Last Answer : a. Operand fields and opcode
Description : _is the step during which a new instruction is read from the memory: a Decode b. Fetch c. Execute d. None of these
Last Answer : b. Fetch
Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read
Last Answer : d. Address register and read
Description : The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, ... incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next
Last Answer : c. Instruction register, incremented and next
Description : Which unit acts as the brain of the computer which control other peripherals and interfaces: a. Memory unit b. Cache unit c. Timing and control unit d. None of these
Last Answer : c. Timing and control unit
Description : Which unit works as an interface between the processor and all the memories on chip or off- chip: a. Timing unit b. Control unit c. Memory control unit d All of these
Last Answer : c. Memory control unit
Description : sis given an instruction in machine language this instruction is fetched from the memory by the CPU to execute: a. ALU b. CPU c. MU d. All of these
Last Answer : b. CPU