EA stands for. a. Effective add b. Effective absolute c. Effective address d. End address

EA stands for.
a. Effective add
b. Effective absolute
c. Effective address
d. End address
by

1 Answer

Answer :

c. Effective address
by

Related questions

In which mode the main memory location holds the EA of the operand: a. Immediate addressing b. Direct addressing c. Register addressing d. Indirect addressing

Description : In which mode the main memory location holds the EA of the operand: a. Immediate addressing b. Direct addressing c. Register addressing d. Indirect addressing

Last Answer : d. Indirect addressing

address is not assigned by linker. a. Absolute b. Relative c. Botha &b a None of these

Description : address is not assigned by linker. a. Absolute b. Relative c. Botha &b a None of these

Last Answer : a. Absolute

address is provided by linker to modules linked together that starting from. | a. Absolute and 0 b. Relative and 0 c. Relative and 1 d. Relative and 3

Description : address is provided by linker to modules linked together that starting from. | a. Absolute and 0 b. Relative and 0 c. Relative and 1 d. Relative and 3

Last Answer : b. Relative and 0

shave addresses where instructions are stored along with address of working storage: a. _ Relative entities b. Absolute entities c. Botha &b d. None of these

Description : shave addresses where instructions are stored along with address of working storage: a. _ Relative entities b. Absolute entities c. Botha &b d. None of these

Last Answer : a. _ Relative entities

Which is addressed by sign extending the 16-bit displacement to 32-bit: a. Memory address b. Effective memory address c. Both a and b d. None of these

Description : Which is addressed by sign extending the 16-bit displacement to 32-bit: a. Memory address b. Effective memory address c. Both a and b d. None of these

Last Answer : b. Effective memory address

Micro-orders generate the_ __ address of operand and execute instruction and prepare for fetching next instruction from the main memory: a. Physical b. Effective c. Logical d. all of above

Description : Micro-orders generate the_ __ address of operand and execute instruction and prepare for fetching next instruction from the main memory: a. Physical b. Effective c. Logical d. all of above

Last Answer : b. Effective

which of the following are types of assembler entities: a. Absolute entities b. Relative entities c. Object program d. Allof these

Description : which of the following are types of assembler entities: a. Absolute entities b. Relative entities c. Object program d. Allof these

Last Answer : d. Allof these

Absolute entitiesare_ Ss whom value signify storage locations that are independent of resulting machine code: a. Numeric constants b. String constants c. Fixed addresses d. Operation codes e. Allofthese

Description : Absolute entitiesare_ Ss whom value signify storage locations that are independent of resulting machine code: a. Numeric constants b. String constants c. Fixed addresses d. Operation codes e. Allofthese

Last Answer : e. Allofthese

A module contains machine code with specification on_ _ a. Relative addresses b. Absolute addresses c. Object program d. None of these

Description : A module contains machine code with specification on_ _ a. Relative addresses b. Absolute addresses c. Object program d. None of these

Last Answer : a. Relative addresses

Abbreviation ASCII stands for: a. American standard code for information interchange b. Abbreviation standard code for information interchange c. Both d. None of these

Description : Abbreviation ASCII stands for: a. American standard code for information interchange b. Abbreviation standard code for information interchange c. Both d. None of these

Last Answer : a. American standard code for information interchange

IR stands for. a. Input representation b. Intermediate representation c. Both d. None

Description : IR stands for. a. Input representation b. Intermediate representation c. Both d. None

Last Answer : b. Intermediate representation

IDE stands for: a. Input device electronics b. Integrated device electronic c. Both d. None

Description : IDE stands for: a. Input device electronics b. Integrated device electronic c. Both d. None

Last Answer : b. Integrated device electronic

ATA stands for. a. Advance technology attachment b. Advance teach attachment c. Both d. None

Description : ATA stands for. a. Advance technology attachment b. Advance teach attachment c. Both d. None

Last Answer : a. Advance technology attachment

SDRAM stands for. a. System dynamic random access memory b. Synchronous dynamic random access memory c. Both d. None

Description : SDRAM stands for. a. System dynamic random access memory b. Synchronous dynamic random access memory c. Both d. None

Last Answer : b. Synchronous dynamic random access memory

SPARC stands for. a. Scalable programmer architecture b. Scalable processor architecture c Scalable point architecture d. None of these

Description : SPARC stands for. a. Scalable programmer architecture b. Scalable processor architecture c Scalable point architecture d. None of these

Last Answer : b. Scalable processor architecture

Markers in subroutine cannot be accepted as limits whereas this markers stands for: a. Top of stack b. Bottom of stack c. Middle of stack d. Allof these

Description : Markers in subroutine cannot be accepted as limits whereas this markers stands for: a. Top of stack b. Bottom of stack c. Middle of stack d. Allof these

Last Answer : a. Top of stack

RPN stands for. a. _ Reverse polish notation b. Read polish notation c. Random polish notation d. None of these

Description : RPN stands for. a. _ Reverse polish notation b. Read polish notation c. Random polish notation d. None of these

Last Answer : a. _ Reverse polish notation

SMP Stands for: a. System multiprocessor b. Symmetric multiprocessor c. Both d. None

Description : SMP Stands for: a. System multiprocessor b. Symmetric multiprocessor c. Both d. None

Last Answer : b. Symmetric multiprocessor

NUMA stands for. a. Number Uniform memory access b. Not Uniform memory access Cc. Non Uniform memory access d. __ Allof these

Description : NUMA stands for. a. Number Uniform memory access b. Not Uniform memory access Cc. Non Uniform memory access d. __ Allof these

Last Answer : a. Number Uniform memory access

SIMD stands for: a. System instruction multiple data b. Single instruction multiple data c. Symmetric instruction multiple data d. Scale instruction multiple data

Description : SIMD stands for: a. System instruction multiple data b. Single instruction multiple data c. Symmetric instruction multiple data d. Scale instruction multiple data

Last Answer : b. Single instruction multiple data

MIMD stands for: a. Multiple input multiple data b. Memory input multiple data c. Multiple instruction multiple data d. Memory instruction multiple data

Description : MIMD stands for: a. Multiple input multiple data b. Memory input multiple data c. Multiple instruction multiple data d. Memory instruction multiple data

Last Answer : c. Multiple instruction multiple data

HLL stands for: a. High level languages b. High level line c. High level logic d. High level limit

Description : HLL stands for: a. High level languages b. High level line c. High level logic d. High level limit

Last Answer : a. High level languages

How many algorithm based on add/subtract and shift category: a. 2 b 64 ec. 8 d 6

Description : How many algorithm based on add/subtract and shift category: a. 2 b 64 ec. 8 d 6

Last Answer : ec. 8

Which are the algorithm based on add/subtract and shift category: a. Restoring division b. Non-restoring division c. SRT division d. Allofthese

Description : Which are the algorithm based on add/subtract and shift category: a. Restoring division b. Non-restoring division c. SRT division d. Allofthese

Last Answer : d. Allofthese

which are of these examples of Intel 8086 opcodes: a. MOV b. ADD c. SUB d. All of these

Description : which are of these examples of Intel 8086 opcodes: a. MOV b. ADD c. SUB d. All of these

Last Answer : d. All of these

The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these

Description : The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these

Last Answer : a. The address of next instruction to be run

The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read

Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read

Last Answer : d. Address register and read

The contents of the program counter isthe __——__—oof the instruction to be run. a. Data b. Address c. Counter d. None of these

Description : The contents of the program counter isthe __——__—oof the instruction to be run. a. Data b. Address c. Counter d. None of these

Last Answer : b. Address

The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, incremented and next b. Instruction register, incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next

Description : The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, ... incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next

Last Answer : c. Instruction register, incremented and next

is a symbolic representation of discrete elements of information: a. Data b. Code c. Address d. Control

Description : is a symbolic representation of discrete elements of information: a. Data b. Code c. Address d. Control

Last Answer : b. Code

Which are the causes of the interrupt: a. In any single device b. In processor poll devices c. In a device whose ID number is stored on the address bus d. Allof these

Description : Which are the causes of the interrupt: a. In any single device b. In processor poll devices c. In a device whose ID number is stored on the address bus d. Allof these

Last Answer : d. Allof these

The register that includes the address of the memory unit is termed asthe _ a. MAR b PC Cc. IR d. None of these

Description : The register that includes the address of the memory unit is termed asthe _ a. MAR b PC Cc. IR d. None of these

Last Answer : a. MAR

In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR

Description : In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR

Last Answer : b. CPU

In memory read the operation puts memory address on to a register known as : a. PC b. ALU ce. MAR d. — Allof these

Description : In memory read the operation puts memory address on to a register known as : a. PC b. ALU ce. MAR d. — Allof these

Last Answer : ce. MAR

Which operation puts memory address in memory address register and data in DR. a Memory read b. Memory write c Both d. None

Description : Which operation puts memory address in memory address register and data in DR. a Memory read b. Memory write c Both d. None

Last Answer : b. Memory write

The memory bus is also referred as _ a. Databus b. Address bus c. Memory bus d. — Allof these

Description : The memory bus is also referred as _ a. Databus b. Address bus c. Memory bus d. — Allof these

Last Answer : a. Databus

By whom address of external function in the assembly source file supplied by __ when activated: a. Assembler b. Linker c. Machine d. Code

Description : By whom address of external function in the assembly source file supplied by __ when activated: a. Assembler b. Linker c. Machine d. Code

Last Answer : b. Linker

___uses the stack to store return address of subroutine: a. CPU b. Microprocessor c. register d. memory

Description : ___uses the stack to store return address of subroutine: a. CPU b. Microprocessor c. register d. memory

Last Answer : b. Microprocessor

When subroutine is called contents of program counter is location address of __ instruction following call instruction is stored on _ __and program execution is transferred to __ address. a. Non executable, pointer and subroutine b. Executable, Stack and Main program Cc. Executable, Queue and Subroutine d. Executable, Stack and Subroutine

Description : When subroutine is called contents of program counter is location address of __ instruction following call instruction is stored on _ __and program execution is transferred to __ address. a. Non ... , Stack and Main program Cc. Executable, Queue and Subroutine d. Executable, Stack and Subroutine

Last Answer : d. Executable, Stack and Subroutine

For each micro operation the control unit generates set of_ signals. a. Control b. Address c. Data d. None of these

Description : For each micro operation the control unit generates set of_ signals. a. Control b. Address c. Data d. None of these

Last Answer : a. Control

How many modes the address in control memory are divided. a 2 b 3 c. 5 d 7

Description : How many modes the address in control memory are divided. a 2 b 3 c. 5 d 7

Last Answer : a 2

Addresses in control memory is made by for each register group: a. Address select logic b. Data select logic c. Control select logic d. All of these

Description : Addresses in control memory is made by for each register group: a. Address select logic b. Data select logic c. Control select logic d. All of these

Last Answer : a. Address select logic

What type of circuit is used by control memory to interconnect registers. a. Data routing circuit b. Address routing circuit c. Control routing circuit d. None of the these

Description : What type of circuit is used by control memory to interconnect registers. a. Data routing circuit b. Address routing circuit c. Control routing circuit d. None of the these

Last Answer : a. Data routing circuit

Copy of data in cache memory is called. a. Datacache b. Execution cache c. Address cache d. Control cache

Description : Copy of data in cache memory is called. a. Datacache b. Execution cache c. Address cache d. Control cache

Last Answer : a. Datacache

In cache memory hit rate indicates. a. Data from requested address is not available b. Data from requested address is available c. Control from requested address is available d. Address from requested address is not available

Description : In cache memory hit rate indicates. a. Data from requested address is not available b. Data from requested address is available c. Control from requested address is available d. Address from requested address is not available

Last Answer : b. Data from requested address is available

In cache memory miss rate indicates. a. Availability of requested data b. Availability of requested address c. Non-Availability of requested data d. Non-Availability of requested address

Description : In cache memory miss rate indicates. a. Availability of requested data b. Availability of requested address c. Non-Availability of requested data d. Non-Availability of requested address

Last Answer : c. Non-Availability of requested data

Invalidation writes only to___ and erases previously residing address in memory: a. Folders b. Memory c. Directory d. Files

Description : Invalidation writes only to___ and erases previously residing address in memory: a. Folders b. Memory c. Directory d. Files

Last Answer : c. Directory

Opcode is the machine instruction obtained from decoding instruction stored in. a. Stack pointer b. Address pointer Cc. Instruction register d. Incrementer

Description : Opcode is the machine instruction obtained from decoding instruction stored in. a. Stack pointer b. Address pointer Cc. Instruction register d. Incrementer

Last Answer : Cc. Instruction register

Various machine level components are: a. Address register > Program counter c Data register d. Accumulator register e. Memory of 2K,16 bits/word RAM f. Multiplexers g. Allof these

Description : Various machine level components are: a. Address register > Program counter c Data register d. Accumulator register e. Memory of 2K,16 bits/word RAM f. Multiplexers g. Allof these

Last Answer : g. Allof these

Source statements consist of 5fields in microinstruction source code are: a. Lable b. Micro-ops c. CD-spec d. BR-spec e. Address f. All of these

Description : Source statements consist of 5fields in microinstruction source code are: a. Lable b. Micro-ops c. CD-spec d. BR-spec e. Address f. All of these

Last Answer : f. All of these