Description : MDR stands for: a. Memory data register b. Memory data recode c. Micro data register d. None of these
Last Answer : a. Memory data register
Description : The information is transferred from the_____ and ____ specified register: a. MDR b. CPU c. Both A and B
Last Answer : c. Both A and B
Description : Which register is used to communicate with memory: a. MAR b. MDR c. Both A and B d. None of these
Description : The information on the data bus is transferred to the ______register: a. MOC b. MDR c. VAM d. CPU
Last Answer : b. MDR
Description : Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these
Last Answer : a. MAR
Description : WE stands for: a. Write enable b. Wrote enable c. Write envy d. None of these
Last Answer : a. Write enable
Description : When the write enable input is not asserted, the gated D latch ______ its output. a. can not change b. clears c. sets d. complements
Last Answer : a. can not change
Description : In modes 2 and 3, if _____ bit of SCON bit is set will causes enable multiprocessor communication and is of ____ bit address. a) SM1, 9EH b) TB8 , 9CH c) SM2 , 9DH d) SM0, 9FH
Last Answer : c) SM2 , 9DH
Description : 8087 connection to 8086, to enable the _________ bank of memory _______pins are to be connected. a) Lower, BHE b) Upper, BHE c) Lower, INT d) Upper, INT.
Last Answer : a) Lower, BHE
Description : Average revenue is calculated by A.TRn - TRn-1 B.P x Q C.TR / MR D.TR / Q
Last Answer : D.TR / Q
Description : ISA stands for: a. Instruct set area b. Instruction set architecture c. Both a and b d. None of these
Last Answer : b. Instruction set architecture
Description : CAD stands for: a. Computer aided drafting b. Compare aided drafting c. Both A and B d. None of these
Last Answer : a. Computer aided drafting
Description : BCD stands for: a. Binary coded decimal b. Based coded decimal c. Both A and B d. None of these
Last Answer : a. Binary coded decimal
Description : MOSFET stands for? a. Metal-oxide-semiconductor field effect transistor b. Metal-oxide-semiconductor fan effort transistor c. Both A and B d. None of these
Last Answer : a. Metal-oxide-semiconductor field effect transistor
Description : HMOS stands for: a. High performance metal oxide semiconductor b. High processor metal oxide semiconductor c. Both A and b d. None of these
Last Answer : a. High performance metal oxide semiconductor
Description : PMOS stands for: a. P-channel metal-oxide-semiconductor b. P-channel memory –oxide-semiconductor c. Both A and B d. None of these
Last Answer : a. P-channel metal-oxide-semiconductor
Description : DMA stands for: a. Dynamic memory access b. Data memory access c. Direct memory access d. Both B and C
Last Answer : d. Both B and C
Description : SAM stands for: a. Simple architecture machine b. Solved architecture machine c. Both a & b d. None of these
Last Answer : a. Simple architecture machine
Description : BCD stands for: a. Binary coded decimal b. Binary coded decoded c. Both a & b d. none of these
Description : CISC stands for: a. Complex instruction set computer b. Camper instruct set of computer c. Compared instruction set computer d. None of these
Last Answer : a. Complex instruction set computer
Description : RISC stands for: a. Reduced Instruction set computer b. Reduced Instruct set compare c. Reduced instruction stands computer d. All of these 107. DEC stands for:
Last Answer : a. Reduced Instruction set computer
Description : VGA stands for: a. Visual graph area b. Visual graphics array c. Visual graph accept d. All of these
Last Answer : b. Visual graphics array
Description : GUI stands for: a. Graphical user interface b. Graph used Intel c. Graphical use inter d. None of these
Last Answer : a. Graphical user interface
Description : NMOS stands for: a. N-channel metal-oxide-semiconductor b. P-channel metal-oxide-semiconductor c. N-channel memory-oxide-semiconductor d. All the above
Last Answer : a. N-channel metal-oxide-semiconductor
Description : RISC stands for: a. Reduced Instruction Set Computer b. Reduced Intergraded Set Computer c. Resource Instruction Set Computer d. Resource Instruction System Computer
Last Answer : a. Reduced Instruction Set Computer
Description : CISC stands for: a. Complex Instruction System Computer b. Complex Instruction Set Car c. Complex Instruction Set Computer d. None of these
Last Answer : c. Complex Instruction Set Computer
Description : CAD stands for a. Computer aided design b. Computer algorithm for design c. Computer application in design d. All of the above
Last Answer : a. Computer aided design
Description : ASCII stands for a. American Stable Code for International Interchange b. American Standard Case for Institutional Interchange c. American Standard Code for Information Interchange d. American Standard Code for Interchange Information
Last Answer : c. American Standard Code for Information Interchange
Description : EBCDIC stands for a. Extended Binary Coded Decimal Interchange Code b. Extended Bit Code Decimal Interchange Code c. Extended Bit Case Decimal Interchange Code d. Extended Binary Case Decimal Interchange Code
Last Answer : a. Extended Binary Coded Decimal Interchange Code
Description : MICR stands for a. Magnetic Ink Character Reader b. Magnetic Ink Code Reader c. Magnetic Ink Cases Reader d. None
Last Answer : a. Magnetic Ink Character Reader
Description : WAN stands for a. Wap Area Network b. Wide Area Network c. Wide Array Net d. Wireless Area Network
Last Answer : b. Wide Area Network
Description : MSI stands for a. Medium Scale Integrated Circuits b. Medium System Integrated Circuits c. Medium Scale Intelligent Circuit d. Medium System Intelligent Circuit
Last Answer : b. Medium System Integrated Circuits
Description : CD-ROM stands for a. Compactable Read Only Memory b. Compact Data Read Only Memory c. Compactable Disk Read Only Memory d. Compact Disk Read Only Memory
Last Answer : d. Compact Disk Read Only Memory
Description : CRT stands for: a. Cathode ray tube b. Compared ray tube c. Command ray tube d. None of these
Last Answer : a. Cathode ray tube
Description : DMA stands for: a. Direct memory access b. Direct memory allocation c. Data memory access d. Data memory allocation
Last Answer : a. Direct memory access
Description : MOC stands for: a. Memory operation complex b. Micro operation complex c. Memory operation complete d. None of these
Last Answer : c. Memory operation complete
Description : VAM stands for: a. Valid memory address b. Virtual memory address c. Variable memory address d. None of these
Last Answer : a. Valid memory address
Description : MAR stands for: a. Memory address register b. Memory address recode c. Micro address register d. None of these
Last Answer : a. Memory address register
Description : CS stands for: a. Cable select b. Chip select c. Control select d. Cable system
Last Answer : b. Chip select
Description : EPROM stands for:
Last Answer : a. Erasable Programmable read-only memory
Description : PROM stands for: a. Programmable read-only memory
Last Answer : a. Programmable read-only memory
Description : MSD stands for: a. Least significant digit b. Most significant digit c. Medium significant digit d. low significant digit
Last Answer : b. Most significant digit
Description : LM stands for: a. Least MAR b. Load MAR c. Least MRA d. Load MRA
Last Answer : b. Load MAR
Description : LA stands for: a. Load accumulator b. Least accumulator c. Last accumulator d. None of these
Last Answer : a. Load accumulator
Description : SP stands for: a. Status pointer b. Stack pointer c. a and b d. None of these
Last Answer : b. Stack pointer
Description : IR stands for: a. Intel register b. In counter register c. Index register d. Instruction register
Last Answer : d. Instruction register
Description : PC stands for: a. Program counter b. Points counter c. Paragraph counter d. Paint counter
Last Answer : a. Program counter
Description : MOS stands for: a. Metal oxide semiconductor b. Memory oxide semiconductor c. Metal oxide select d. None of these
Last Answer : a. Metal oxide semiconductor
Description : How do the contents of the MAR and MDR registers changes during the fetch decode execute cycle?
Last Answer : Need answer
Description : In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR
Last Answer : b. CPU