Description : If ______ and ________ connections are made so that an error condition in 8087 can interrupt to the processor. a) BHE, RQ/GT1 b) BUSY, TEST c) INT, NMI d) RQ/GT0, RQ/GT1
Last Answer : c) INT, NMI
Description : BHE of 8086 microprocessor signal is used to interface the a) Even bank memory b) Odd bank memory c) I/O d) DMA
Last Answer : b) Odd bank memory
Description : ______ input is available, so that another coprocessor can be connected and function in _________ with the 8087. . a) RQ/GT0, parallel b) RQ/GT1, parallel c) QS1 & QS0, parallel d) S0 & S1, parallel.
Last Answer : a) RQ/GT0, parallel
Description : In 8087, _______ many register stack are there? And of _____ registers. These registers are used as _________ stack. a) 7, 40 bit, FIFO. b) 8, 60 bit, LILO. c) 8, 80 bit, LIFO d) 7, 80 bit, FILO.
Last Answer : b) 8, 60 bit, LILO.
Description : Which processor provided 1 MB memory: a. 16-bit 8086 and 8088 b. 32-bit 8086 and 8088 c. 64-bit 8086 and 8088 d. 8-bit 8086 and 8088
Last Answer : a. 16-bit 8086 and 8088
Description : Define memory segmentation. How memory segmentation is achieved in 8086? State advantages of memory segmentation.
Last Answer : Memory Segmentation: The memory in an 8086 microprocessor is organized as a segmented memory. The physical memory is divided into 4 segments namely, - Data segment, Code Segment, Stack Segment and Extra ... 16 bit size. 6) Programs and data can be stored separately from each other in segmentation.
Description : One of the following signals belongs to the 8087 coprocessor is a. HOLD b. BUSY c. TEST d. NMI
Last Answer : c. TEST
Description : In 8087 coprocessor one of the following instructions is not valid a. FSIN b. FPTAN c. FIDIV d. FSQRT
Last Answer : a. FSIN
Description : Which of the following is of compare instruction in 8087? a) FTST b) FPREM c) FPATAN d) FLDI
Last Answer : a) FTST
Description : In 8087, which instruction is used for division real reversed______. a) FDIV b) FIDIVR c) FDIVR d) FDIVRP
Last Answer : c) FDIVR
Description : Why 8087 is referred to as Coprocessor? i) Because 8087 is used in parallel with main processor in a system, rather than serving as a main processor itself. ii) Because 8087 is used in serial with main processor in a ... math computations. a) i & iii b) ii & iii c) iii only. d) i only.
Last Answer : c) iii only.
Description : ___ Connection and the _______ instruction will solve the problem of synchronization between processor and coprocessor. a) INT & NMI, WAIT b) RQ/GT0 & RQ/GT1, FWAIT c) BUSY & TEST, FWAIT d) S0 & QS0, WAIT
Last Answer : b) RQ/GT0 & RQ/GT1, FWAIT
Description : Who was introduce the 80286 microprocessor updated on 8086,in 1983: a. Intel b. Motorola c. Fairchild d. None of these
Last Answer : a. Intel
Description : How many speed of 8088,8085,8086 microprocessor: a. 2.5 Million instruction per second b. 1.5 Million instruction per second c. 3.5 Million instruction per second d. 1.6 Million instruction per second
Last Answer : a. 2.5 Million instruction per second
Description : Which is 16 Bit microprocessor: a. 8088 b. 8086 c. 8085 d. All of these
Last Answer : d. All of these
Description : Intel used HMOS technology to recreate_____: a. 8084 A b. 8086 A c. 8085 A d. 8088 A
Last Answer : c. 8085 A
Description : In 8086 microprocessor one of the following instructions is executed before an arithmeticoperation a. AAM b) AAD c) DAS d) DAA
Last Answer : b) AAD
Description : .How many transistors does the 8086 have?a) 10,000b ) 29,000 c) 110,000d) 129,000
Last Answer : ) 29,000
Description : In 8086 microprocessor one of the following statements is not true.a)Coprocessor is interfaced in MAX mode b)Coprocessor is interfaced in MIN mode c)I/O can be interfaced in MAX / MIN moded)Supports pipelining
Last Answer : b)Coprocessor is interfaced in MIN mode
Description : 8086 is interfaced to two 8259s (Programmable interrupt controllers). If 8259s are in master slave configuration the number of interrupts available to the 8086 microprocessor is a) 8 b) 16 c) 15 d) 64
Last Answer : a) 8
Description : 8086 microprocessor is interfaced to 8253 a programmable interval timer. The maximum number by which the clock frequency on one of the timers is divided by a) 216 b) 28 c) 210 d) 220
Last Answer : d) 220
Description : In 8086 microprocessor one of the following instructions is executed before an arithmetic operation a) AAM b) AAD c) DAS d) DAA
Description : What is the output of the following code AL=00110101 BL= 39H M. Krishna Kumar/IISc. Bangalore M2/V1/June 04/1 Microprocessors and Microcontrollers/Assembly language of 8086 Multiple Choice Questions SUB AL, BL AAS ... , CF=1 b) BL=00000100, CF=0 c) AL=11111100 CF=1 d) BL= 00000100, CF=1
Last Answer : b) BL=00000100, CF=0
Description : 8088 microprocessor differs with 8086 microprocessor in a) Data width on the output b) Address capability c) Support of coprocessor d) Support of MAX / MIN mode
Last Answer : a) Data width on the output
Description : In 8086 microprocessor one of the following statements is not true. a) Coprocessor is interfaced in MAX mode b) Coprocessor is interfaced in MIN mode c) I/O can be interfaced in MAX / MIN mode
Last Answer : b) Coprocessor is interfaced in MIN mode
Description : n 8086 microprocessor the following has the highest priority among all type interrupts. a) NMI b) DIV 0 c) TYPE 255 d) OVER FLOW
Last Answer : a) NMI
Description : In 8086 the overflow flag is set when a) The sum is more than 16 bits b) Signed numbers go out of their range after an arithmetic operation c) Carry and sign flags are set
Last Answer : b) Signed numbers go out of their range after an arithmetic operation
Description : In 8086, Example for Non maskable interrupts are a) Trapb) RST6.5 c) INTR
Last Answer : a) Trap
Description : Write an algorithm to subtract two 16 bit numbers (With borrow) in 8086 microprocessor.
Last Answer : Algorithm for 16 bit numbers subtraction with borrow: 1. Load 0000H into CX register (for borrow) 2. Load the first number into AX(accumulator) 3. Load the second number into BX register 4. Subtract ... . Move data from AX(accumulator) to memory 8. Move data from CX register to memory 9. Stop
Description : Enlist any four addressing modes of 8086 microprocessor.
Last Answer : Addressing modes of 8086 : 1. Immediate 2. Direct 3. Register 4. Register indirect 5. Indexed 6. Register relative 7. Based indexed 8. Relative based indexed 9. Implied
Description : State the use of OF and DF flags of 8086 microprocessor.
Last Answer : Overflow Flag: This flag is set if an overflow occurs, i.e. if the result of a signed operation is large enough to be accommodated in destination register. Direction Flag: It selects either increment or decrement mode for DI &/or SI register during string instructions.
Description : Describe the functions of General purpose registers of 8086 microprocessor.
Last Answer : (i) General Purpose Registers of 8086 1. AX (Accumulator) - Used to store the result for arithmetic / logical operations All I/O data transfer using IN & OUT instructions use A ... Index - acts as the destination for string movement instructions Used to hold offset address of Extra segment.
Description : The 16 bit flag of 8086 microprocessor is responsible to indicate ___________ A. the condition of result of ALU operation B. the condition of memory C. the result of addition D. the result of subtraction
Last Answer : The 16 bit flag of 8086 microprocessor is responsible to indicate the condition of result of ALU operation
Description : In 8086 microprocessor , the address bus is ________ bit wide A. 12 bit B. 10 bit C. 16 bit D. 20 bit
Last Answer : In 8086 microprocessor, the address bus is 20 bit
Description : The intel 8086 microprocessor is a _______ processor A. 8 bit B. 16 bit C. 32 bit D. 4 bit
Last Answer : The intel 8086 microprocessor is a 16 bit processor
Description : The upper red arrow show that CPU sends out the control signals____ and _____ indicate the data is read from the memory: a. Memory request b. Read c. Both A and B d. None of these
Last Answer : c. Both A and B
Description : A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above
Last Answer : b. Address bus
Description : When the write enable input is not asserted, the gated D latch ______ its output. a. can not change b. clears c. sets d. complements
Last Answer : a. can not change
Description : WE stands for: a. Write enable b. Wrote enable c. Write envy d. None of these
Last Answer : a. Write enable
Description : ED stands for: a. Enable MRD b. Enable MDR c. Both a and b d. None of these
Last Answer : b. Enable MDR
Description : In modes 2 and 3, if _____ bit of SCON bit is set will causes enable multiprocessor communication and is of ____ bit address. a) SM1, 9EH b) TB8 , 9CH c) SM2 , 9DH d) SM0, 9FH
Last Answer : c) SM2 , 9DH
Description : Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these
Last Answer : a. MAR
Description : A type of core store that has a lower access time than the devices used for working store in the same processor is known as a. Core memory b. Buffer c. Fast core d. Address register
Last Answer : d. Address register
Description : The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus
Last Answer : a. Address bus
Description : All keywords in Python are in _________ a) lower case b) UPPER CASE c) Capitalized d) None of the mentioned
Last Answer : Answer: d Explanation: True, False and None are capitalized while the others are in lower case.
Description : To read or write a complete word from / to the memory in 8086 microprocessor and if it is located at an even address, the number of Read or Write cycles required is
Last Answer : To read or write a complete word from / to the memory in 8086 microprocessor and if it is located at an even address, the number of Read or Write cycles required is one
Description : The 8086 fetches instruction one after another from _____ of memory. (a) Code segment (b) IP (c) ES (d) SS
Last Answer : Code segemnt
Description : In 8279, the keyboard entries are debounced and stored in an _________, that is further accessed by the CPU to read the key codes. a) 8-bit FIFO b) 8-byte FIFO c) 16 byte FIFO d) 16 bit FIFO
Last Answer : b) 8-byte FIFO
Description : belt of silk runs over two metal pulleys, one of which is surrounded by a hollow metal sphere. Two electrodes, in the form of comb-shaped rows of sharp metal points, are positioned ... potential is applied to the upper pulley. A simple version of which equipment is being described here?
Last Answer : Van de Graaff generator.
Description : Offline device is a. A device which is not connected to CPU b. A device which is connected to CPU c. A direct access storage device d. An I/O device
Last Answer : a. A device which is not connected to CPU