Description : It contains the stack for PC storage during subroutine calls and input/output interrupt services: a. Seven- level hardware b. Eight- level hardware
Last Answer : b. Eight- level hardware
Description : Which are benefit of input/output interrupt: a. It is an external analogy to exceptions b. The processor initiates and perform all I/O operation c. The data is transferred into the memory through interrupt handler d. = Alllof these
Last Answer : d. = Alllof these
Description : Which are contains one or more register that may be referenced by machine instruction: a. Input b. Output c. CPU d. ALU
Last Answer : c. CPU
Description : __is the sequence of operations performed by CPU in processing an instruction: a. Execute cycle b. Fetch cycle c. Decode d. Instruction cycle
Last Answer : d. Instruction cycle
Description : Which interrupt services save all the register and flags. a. Save interrupt b. Input/output interrupt c. Service interrupt d. All of these
Last Answer : b. Input/output interrupt
Description : Which instruction are arranged as per the protocols of memory reference format of the input file in a simple ASCII sequence of integers between the range O to 99 separated by spaces without formatted text ... : a. Memory reference instruction b. Memory reference format c. Both d. None of these
Last Answer : a. Memory reference instruction
Description : Which are the not causes of the interrupt: a. In any single device b. In processor poll devices c. Itis an external analogy to exception d. None of these
Last Answer : c. Itis an external analogy to exception
Description : The instruction set can have variable-length instruction format primarily due to: a. Varying number of operands b. Varying length of opcodes in some CPU ce. Both d. None
Last Answer : ce. Both
Description : An __ -0 option is used for. a. Input file b. External file c. Output file d. None of these
Last Answer : c. Output file
Description : sis given an instruction in machine language this instruction is fetched from the memory by the CPU to execute: a. ALU b. CPU c. MU d. All of these
Last Answer : b. CPU
Description : Which cycle refers to the time period during which one instruction is fetched and executed by the CPU: a. Fetch cycle b. Instruction cycle c. Decode cycle d. Execute cycle
Last Answer : b. Instruction cycle
Description : Which is the most important component of a digit computer that interprets the instruction and processes the data contained in computer programs: MU b. ALU c. CPU d. PC
Description : Modern assemblers for RISC based architectures make optimization of instruction scheduling to make use of CPU __ efficiently: a. Pipeline b. Without pipeline c. Botha &b d. None of these
Last Answer : a. Pipeline
Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU
Last Answer : b. Main memory
Description : Which section is basically a sequence of instruction with a clear indication of beginning and end for updating shared variables. a. Racing section b. Critical section c. d. Both None of thes
Last Answer : . Critical sectio
Description : The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these
Last Answer : a. The address of next instruction to be run
Description : In instruction formats instruction is represent by a___ _ of bits: a. Sequence b. Parallel c. Both d. None
Last Answer : a. Sequence
Description : In program control the instruction is set for the statement in a: a. Parallel b. Sequence c. Both d. None
Last Answer : b. Sequence
Description : Which are the causes of the interrupt: a. In any single device b. In processor poll devices c. In a device whose ID number is stored on the address bus d. Allof these
Last Answer : d. Allof these
Description : __is divided into a number of fields and is represented as a sequence of bits: a. instruction b. — instruction set c. instruction code d. parity code
Last Answer : a. instruction
Description : Which functions are performed by CU: a. Data exchange b/w CPU and memory or I/O modules b. External operations c. Internal operations inside CPU d Botha&c
Last Answer : d Botha&c
Description : ___is the data paths link CPU registers with memory or I/O modules. a. External data paths b. Internal data paths c. Boreal data paths d. Exchange data paths
Last Answer : a. External data paths
Description : Which is the input of control unit: a. Master clock signal b. Instruction register c. Flags d. Control signals from bus e. Allof these
Last Answer : e. Allof these
Description : MIMD stands for: a. Multiple input multiple data b. Memory input multiple data c. Multiple instruction multiple data d. Memory instruction multiple data
Last Answer : c. Multiple instruction multiple data
Description : Sequence of microinstructions is termed as micro program or a. Hardware b. Software c. Firmware d. None of these
Last Answer : c. Firmware
Description : A CPU handles interrupt by executing interrupt service subroutine................. (A) by checking interrupt register after execution of each instruction (B) by checking interrupt register ... cycle (C) whenever an interrupt is registered (D) by checking interrupt register at regular time interval
Last Answer : (A) by checking interrupt register after execution of each instruction
Description : Which are the functioning of I/O interrupt: a. The processor organizes all the I/O operation for smooth functioning b. After completing the I/O operation the device interrupt the processor c. Both d. None of these
Last Answer : b. After completing the I/O operation the device interrupt the processor
Description : The bits are shifted and the first flip-flop receives its binary information from the____ a. Serial output b. Serial input c. Both d. None
Last Answer : b. Serial input
Description : Memory —mapped ___is used this is just another memory address. a. Input b. Output c. Both d. None
Last Answer : c. Both
Description : IRET stand for. a. Interrupt enter b. Interrupt return c. Interrupt delete d. None of these
Last Answer : b. Interrupt return
Description : which of the following is interrupt mode. a. Task mode b. Executive mode c. Botha &b d. None of these
Last Answer : b. Executive mode
Description : Interrupt which arises from illegal or erroneous use of an instruction or data is (A) Software interrupt (B) Internal interrupt (C) External interrupt (D) All of the above
Last Answer : (B) Internal interrupt
Description : Which register holds the current instruction to be executed. a. Instruction register b. Program register 9 Control register a None of these
Last Answer : a. Instruction register
Description : Which unit is comparable to the central nervous system in the human body: a. Output unit b. Control unit c. Input unit d. All of these
Last Answer : b. Control unit
Description : If we define putchar function in putchar :. char -> IO () syntax than character input as an argument andreturns a. Useful value b. Get output c. Getno output d. None of these
Last Answer : c. Getno output
Description : The front panel display provides lights as green LED represent sand red LED represent _ for device programmer who writes input/output basic: a. Busy and Error b. Error and Busy c. Busy and Busy d. Error and Error
Last Answer : a. Busy and Error
Description : The processed data is sent for output to standard __ device which by default is computer screen: a. Input b. Output c. Botha &b d. None of these
Last Answer : b. Output
Description : is the step during which the operations specified by the instruction are executed: a. Execute b. Decode c. Both a& b d. None of these
Last Answer : a. Execute
Description : Execution of instruction specified by instruction to perform: a. Operation b. Operands c. Both a &b d. None of these
Last Answer : a. Operation
Description : Which unit is necessary for the execution of instruction: a. Timing b. Control ce. Both d. None of these
Description : Which instruction are 32 bits long , with extra 16 bits. a. Memory reference instruction b. Memory reference format c. Both d. None of these
Description : Which are instruction in which two machine cycle are required: a. Instruction cycle b. Memory reference instruction c. Both d. None of these
Last Answer : b. Memory reference instruction
Description : Which instruction are used in multithreaded parallel processor architecture. a. Memory reference instruction b. Memory reference format c. Both d. None of these
Description : Each instruction is also accompanied by a___ : a. Microprocessor b. Microcode c. Both d. None of these
Last Answer : b. Microcode
Description : The length of instruction set depends on: a. Data size b. Memory size c. Both d. None
Last Answer : b. Memory size
Description : In length instruction some programs wants a complex instruction set containing more instruction, more addressing modes and greater address rang, as in case of a. RISC b. CISC c. Both d. None
Last Answer : b. CISC
Description : In length instruction other programs on the other hand, want a small and fixed-size instruction set that contains only a limited number of opcodes, as in case of a. RISC b CISC c. Both d. None
Last Answer : a. RISC
Description : An instruction code must specify the address of the__. a. Opecode b. Operand c. Both d. None
Last Answer : b. Operand
Description : Arithmetic instruction are used to perform operation on: a. Numerical data b. Non-numerical data c. Both d. None
Last Answer : a. Numerical data
Description : Which processor has a single instruction multiple data stream organization that manipulates the common instruction by means of multiple functional units. a. Attached array processor b. SIMD array processor c. Both d. None
Last Answer : b. SIMD array processor