Description : shave addresses where instructions are stored along with address of working storage: a. _ Relative entities b. Absolute entities c. Botha &b d. None of these
Last Answer : a. _ Relative entities
Description : Modern assemblers for RISC based architectures make optimization of instruction scheduling to make use of CPU __ efficiently: a. Pipeline b. Without pipeline c. Botha &b d. None of these
Last Answer : a. Pipeline
Description : Return instruction is written in_ to written to main program: a. Subroutine b. Main program c. Botha &b d. None of these
Last Answer : a. Subroutine
Description : IBM-360 type language is example which supporting _—___—sJanguage. a. Micro b. Macro c. Botha &b d. None of these
Last Answer : b. Macro
Description : In protocol each process can make a request onlyinan a. Increasing order b. Decreasing order c. Botha &b d. None of these
Last Answer : a. Increasing order
Description : Which state refers to a state that is not safe not necessarily a deadlocked state. a. Safe state b. Unsafe state c. Botha &b d. None of these
Last Answer : b. Unsafe state
Description : Which is one of the important I/O devices and is most commonly used as permanent storage device in any processor: a. Soft disk b. Hard disk c. Botha &b d. None of these
Last Answer : b. Hard disk
Description : which of the 2 files are created by the assembler. a. _ List and object file b. Link and object file c. Botha &b d. None of these
Last Answer : a. _ List and object file
Description : Ingiven lines of code MOV AX,BL have different type of operands according to assembler for 8086 architecture these identifiers must be of. a. Different type only in byte b. Same type either in word or byte c. Botha &b d. None of these
Last Answer : b. Same type either in word or byte
Description : address is not assigned by linker. a. Absolute b. Relative c. Botha &b a None of these
Last Answer : a. Absolute
Description : Full form of MIPS assembler is: a. Microprocessor without interlocked pipeline stage b. Microprocessor with interlocked pipeline stage c. Botha &b d. None of these
Last Answer : a. Microprocessor without interlocked pipeline stage
Description : Ina complex program, the overlaps: a. Branching b. Condition c. Botha &b d. None of these
Last Answer : a. Branching
Description : Avoid crossing flow lines. a. Flowchart b. Algorithm c. Botha &b d. None of these
Last Answer : a. Flowchart
Description : is useful to prepare detailed program documentation: a. Flowchart b. Algorithm c. Botha &b d. None of these
Description : Cache memory is located between main memory and : a. CPU b. Memory c. Botha &b d. None of these
Last Answer : a. CPU
Description : subroutine declaration come after procedure announcement: a. Global b. Local c. Botha &b d. None of these
Last Answer : a. Global
Description : Callis_ subroutine call. a. Conditional b. Unconditi c. Botha &b d. None of these
Last Answer : b. Unconditi
Description : The processed data is sent for output to standard __ device which by default is computer screen: a. Input b. Output c. Botha &b d. None of these
Last Answer : b. Output
Description : which of the following is interrupt mode. a. Task mode b. Executive mode c. Botha &b d. None of these
Last Answer : b. Executive mode
Description : is the step during which the operations specified by the instruction are executed: a. Execute b. Decode c. Both a& b d. None of these
Last Answer : a. Execute
Description : The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these
Last Answer : a. The address of next instruction to be run
Description : getchar :: IO char in this given function what is indicated by IO char: a. when getchar is invoked it returns a character b. when getchar is executed it returns a character c. botha & b d. none of these
Last Answer : a. when getchar is invoked it returns a character
Description : Execution of instruction specified by instruction to perform: a. Operation b. Operands c. Both a &b d. None of these
Last Answer : a. Operation
Description : state keeps track of position related to execution of an instruction: a. Major b. Minor c. Botha & b d. None of these
Last Answer : a. Major
Description : A computer having writable control memory is known as_ a. Static micro programmable b. Dynamic micro programmable c. Botha & b d. None of these
Last Answer : b. Dynamic micro programmable
Description : Suppose that the number of instructions executed between page faults is directly proportional to the number of page frames allocated to a program. If the available memory is doubled, the mean interval between page faults is also ... memory were available? (A) 60 sec (B) 30 sec (C) 45 sec (D) 10 sec
Last Answer : Answer: C Explanation: T = Ninstr x 1µs + 15,000 x 2,000 µs = 60s Ninstr x 1µs = 60,000,000 µs - 30,000,000 µs = 30,000,000 µs Ninstr = 30,000,000 The number of instruction ... doesn't mean that the program runs twice as fast as on the first system. Here, the performance increase is of 25%.
Description : _is sequence of instructions is executed and repeated any no. of times in loop until logical condition is true: a. Iteration b. Repetition c Botha&b d. None of these
Last Answer : c Botha&b
Description : Which cycle refers to the time period during which one instruction is fetched and executed by the CPU: a. Fetch cycle b. Instruction cycle c. Decode cycle d. Execute cycle
Last Answer : b. Instruction cycle
Description : Which register holds the next instruction to be executed:
Last Answer : c. Program control register
Description : Which register holds the current instruction to be executed. a. Instruction register b. Program register 9 Control register a None of these
Last Answer : a. Instruction register
Description : Which is the method by which instructions are selected for execution: a. Instruction selection b. — Selection control c. Instraction sequencing d. All of these
Last Answer : c. Instraction sequencing
Description : Decoding of an instruction in RISC architecture means decision on working of control unit for: a. Remainder of instructions b. _ Divisor of instructions c. Dividend of instructions d. None of these
Last Answer : a. Remainder
Description : Which is data manipulation types are. a. Arithmetic instruction b. Shift instruction c. Logical and bit manipulation instructions d. All of these
Last Answer : d. All of these
Description : Micro-orders generate the_ __ address of operand and execute instruction and prepare for fetching next instruction from the main memory: a. Physical b. Effective c. Logical d. all of above
Last Answer : b. Effective
Description : __is the sequence of operations performed by CPU in processing an instruction: a. Execute cycle b. Fetch cycle c. Decode d. Instruction cycle
Last Answer : d. Instruction cycle
Description : Sequence of microinstructions is termed as micro program or a. Hardware b. Software c. Firmware d. None of these
Last Answer : c. Firmware
Description : Which micro operations carry information from one register to another. a. Register transfer b. Arithmetic c. Logical d. — Allof these
Last Answer : a. Register transfer
Description : Which memory is assembled between main memory and CPU: a. Primary memory b. Cache memory Cc. Botha & b d. None of these
Last Answer : b. Cache memory
Description : function is used to transfer the control to end of a program which uses one argument( ) and takes value is zero for_ __ termination and non-zero for _termination: a. _ Exit( ) normal, abnormal b. Break, normal, abnormal Botha & b None of these
Last Answer : a. _ Exit( ) normal, abnormal
Description : For each micro operation the control unit generates set of_ signals. a. Control b. Address c. Data d. None of these
Last Answer : a. Control
Description : The complete set of op-codes for a particular microprocessor defines the_ set for that processor: a. Code b. Function c. Module d. Instruction
Last Answer : d. Instruction
Description : __is divided into a number of fields and is represented as a sequence of bits: a. instruction b. — instruction set c. instruction code d. parity code
Last Answer : a. instruction
Description : One of use of microprogramming to implement _ ____ of processor in Intel 80x86 and Motorola 680x0 processors whose instruction set are evolved from 360 original. a. Control structure b. Without control c. Control unit d. Only control
Last Answer : c. Control unit
Description : In data transfer manipulation designing as instruction set for a system isa complex_ a. Art b. System Cc. Computer d. None of these
Last Answer : a. Art
Description : The length of instruction set depends on: a. Data size b. Memory size c. Both d. None
Last Answer : b. Memory size
Description : In length instruction some programs wants a complex instruction set containing more instruction, more addressing modes and greater address rang, as in case of a. RISC b. CISC c. Both d. None
Last Answer : b. CISC
Description : In length instruction other programs on the other hand, want a small and fixed-size instruction set that contains only a limited number of opcodes, as in case of a. RISC b CISC c. Both d. None
Last Answer : a. RISC
Description : The instruction set can have variable-length instruction format primarily due to: a. Varying number of operands b. Varying length of opcodes in some CPU ce. Both d. None
Last Answer : ce. Both
Description : In program control the instruction is set for the statement in a: a. Parallel b. Sequence c. Both d. None
Last Answer : b. Sequence
Description : Each instruction is also accompanied by a___ : a. Microprocessor b. Microcode c. Both d. None of these
Last Answer : b. Microcode