Which cycle refers to the time period during which one instruction is fetched and executed by the CPU: a. Fetch cycle b. Instruction cycle c. Decode cycle d. Execute cycle

Which cycle refers to the time period during which one instruction is fetched and executed by the CPU:

a. Fetch cycle
b. Instruction cycle
c. Decode cycle
d. Execute cycle
by

1 Answer

Answer :

b. Instruction cycle
by

Related questions

__is the sequence of operations performed by CPU in processing an instruction: a. Execute cycle b. Fetch cycle c. Decode d. Instruction cycle

Description : __is the sequence of operations performed by CPU in processing an instruction: a. Execute cycle b. Fetch cycle c. Decode d. Instruction cycle

Last Answer : d. Instruction cycle

_is the step during which a new instruction is read from the memory: a Decode b. Fetch c. Execute d. None of these

Description : _is the step during which a new instruction is read from the memory: a Decode b. Fetch c. Execute d. None of these

Last Answer : b. Fetch

is the step during which the operations specified by the instruction are executed: a. Execute b. Decode c. Both a& b d. None of these

Description : is the step during which the operations specified by the instruction are executed: a. Execute b. Decode c. Both a& b d. None of these

Last Answer : a. Execute

sis given an instruction in machine language this instruction is fetched from the memory by the CPU to execute: a. ALU b. CPU c. MU d. All of these

Description : sis given an instruction in machine language this instruction is fetched from the memory by the CPU to execute: a. ALU b. CPU c. MU d. All of these

Last Answer : b. CPU

Pipeline implement a. fetch instruction b. decode instruction c. fetch operand d. calculate operand e. execute instruction f. all of abve

Description : Pipeline implement a. fetch instruction b. decode instruction c. fetch operand d. calculate operand e. execute instruction f. all of abve

Last Answer : f. all of abve

How do the contents of the MAR and MDR registers changes during the fetch decode execute cycle?

Description : How do the contents of the MAR and MDR registers changes during the fetch decode execute cycle?

Last Answer : Need answer

Jump has 3 major states are: a. Fetch b. Decode c. Complete d= Allof these

Description : Jump has 3 major states are: a. Fetch b. Decode c. Complete d= Allof these

Last Answer : d= Allof these

Decode is the step during which instruction is__ a. Initialized b. Incremented c. Decoded d. Bothb&c

Description : Decode is the step during which instruction is__ a. Initialized b. Incremented c. Decoded d. Bothb&c

Last Answer : c. Decoded

A computer executes programs in the sequence of : (1) Execute, Fetch, Decode (2) Store, Fetch, Execute (3) Fetch, Decode, Execute (4) Decode, Fetch, Execute

Description : A computer executes programs in the sequence of : (1) Execute, Fetch, Decode (2) Store, Fetch, Execute (3) Fetch, Decode, Execute (4) Decode, Fetch, Execute

Last Answer : Fetch, Decode, Execute

Who is the represents the fundamental process in the operation of the CPU: a. The fetch-execute cycle and pipelining b. The assembly c. Both A and B d. None of these

Description : Who is the represents the fundamental process in the operation of the CPU: a. The fetch-execute cycle and pipelining b. The assembly c. Both A and B d. None of these

Last Answer : a. The fetch-execute cycle and pipelining

The time required to complete one instruction is called. a. Fetch time b. Execution time c. Control time d. All of these

Description : The time required to complete one instruction is called. a. Fetch time b. Execution time c. Control time d. All of these

Last Answer : b. Execution time

The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read

Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read

Last Answer : d. Address register and read

A CPU handles interrupt by executing interrupt service subroutine................. (A) by checking interrupt register after execution of each instruction (B) by checking interrupt register at the end of the fetch cycle (C) whenever an interrupt is registered (D) by checking interrupt register at regular time interval

Description : A CPU handles interrupt by executing interrupt service subroutine................. (A) by checking interrupt register after execution of each instruction (B) by checking interrupt register ... cycle (C) whenever an interrupt is registered (D) by checking interrupt register at regular time interval

Last Answer : (A) by checking interrupt register after execution of each instruction

Micro-orders generate the_ __ address of operand and execute instruction and prepare for fetching next instruction from the main memory: a. Physical b. Effective c. Logical d. all of above

Description : Micro-orders generate the_ __ address of operand and execute instruction and prepare for fetching next instruction from the main memory: a. Physical b. Effective c. Logical d. all of above

Last Answer : b. Effective

Which of the following 2 task are performed to execute an instruction by MCU: a. Microinstruction execution b. Microinstruction sequencing c. Botha&b d. None of these

Description : Which of the following 2 task are performed to execute an instruction by MCU: a. Microinstruction execution b. Microinstruction sequencing c. Botha&b d. None of these

Last Answer : c. Botha&b

Which register holds the next instruction to be executed:

Description : Which register holds the next instruction to be executed:

Last Answer : c. Program control register

Which register holds the current instruction to be executed. a. Instruction register b. Program register 9 Control register a None of these

Description : Which register holds the current instruction to be executed. a. Instruction register b. Program register 9 Control register a None of these

Last Answer : a. Instruction register

Each instruction is executed by set of micro operations termed as. a. Micro instructions b. Mini instructions c. Botha &b d. None of these

Description : Each instruction is executed by set of micro operations termed as. a. Micro instructions b. Mini instructions c. Botha &b d. None of these

Last Answer : a. Micro instructions

is an external hardware event which causes the CPU to interrupt the current instruction sequence: a. Input interrupt b. Output interrupt c. Both d. None of these

Description : is an external hardware event which causes the CPU to interrupt the current instruction sequence: a. Input interrupt b. Output interrupt c. Both d. None of these

Last Answer : c. Both

Which is the most important component of a digit computer that interprets the instruction and processes the data contained in computer programs: MU b. ALU c. CPU d. PC

Description : Which is the most important component of a digit computer that interprets the instruction and processes the data contained in computer programs: MU b. ALU c. CPU d. PC

Last Answer : c. CPU

Modern assemblers for RISC based architectures make optimization of instruction scheduling to make use of CPU __ efficiently: a. Pipeline b. Without pipeline c. Botha &b d. None of these

Description : Modern assemblers for RISC based architectures make optimization of instruction scheduling to make use of CPU __ efficiently: a. Pipeline b. Without pipeline c. Botha &b d. None of these

Last Answer : a. Pipeline

Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU

Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU

Last Answer : b. Main memory

Which are contains one or more register that may be referenced by machine instruction: a. Input b. Output c. CPU d. ALU

Description : Which are contains one or more register that may be referenced by machine instruction: a. Input b. Output c. CPU d. ALU

Last Answer : c. CPU

The instruction set can have variable-length instruction format primarily due to: a. Varying number of operands b. Varying length of opcodes in some CPU ce. Both d. None

Description : The instruction set can have variable-length instruction format primarily due to: a. Varying number of operands b. Varying length of opcodes in some CPU ce. Both d. None

Last Answer : ce. Both

In which addressing the simplest addressing mode where an operand is fetched from memory is a. Immediate addressing b. Direct addressing c. Register addressing d. None of these

Description : In which addressing the simplest addressing mode where an operand is fetched from memory is a. Immediate addressing b. Direct addressing c. Register addressing d. None of these

Last Answer : b. Direct addressing

What is the control unit's function in the CPU? a. To transfer data to primary storage b. to store program instruction c. to perform logic operations d. to decode program instruction

Description : What is the control unit's function in the CPU? a. To transfer data to primary storage b. to store program instruction c. to perform logic operations d. to decode program instruction

Last Answer : b. to store program instruction

The fetch-execute cycle is to use a system know as: a. Assembly line b. Pipelining c. Cache d. None of these

Description : The fetch-execute cycle is to use a system know as: a. Assembly line b. Pipelining c. Cache d. None of these

Last Answer : b. Pipelining

How can we make computers work faster? a. The fetch-execute cycle and pipelining b. The assembly c. Both A and B d. None of these

Description : How can we make computers work faster? a. The fetch-execute cycle and pipelining b. The assembly c. Both A and B d. None of these

Last Answer : a. The fetch-execute cycle and pipelining

The necessary steps carried out to perform the operation of accessing either memory or I/O Device, constitute a ___________________ a) fetch operation b) execute operation c) machine cycle

Description : The necessary steps carried out to perform the operation of accessing either memory or I/O Device, constitute a ___________________ a) fetch operation b) execute operation c) machine cycle

Last Answer : c) machine cycle

In second pass, assembler creates _ in binary format for every instruction in program and then refers to the symbol table to giving every symbol an_ _ relating the segment. a. Code and program b. Program and instruction c. Code and offset d. All of these

Description : In second pass, assembler creates _ in binary format for every instruction in program and then refers to the symbol table to giving every symbol an_ _ relating the segment. a. Code and program b. Program and instruction c. Code and offset d. All of these

Last Answer : c. Code and offset

Which are instruction in which two machine cycle are required: a. Instruction cycle b. Memory reference instruction c. Both d. None of these

Description : Which are instruction in which two machine cycle are required: a. Instruction cycle b. Memory reference instruction c. Both d. None of these

Last Answer : b. Memory reference instruction

A query fetched 10 records How many times does a PRE- QUERY Trigger and POST-QUERY Trigger will get executed ?

Description : A query fetched 10 records How many times does a PRE-QUERY Trigger and POST-QUERY Trigger will get executed ?

Last Answer : PRE-QUERY fires once. POST-QUERY fires 10 times.

The act of acquiring an instruction is referred as the____ the instruction: a. Fetching b. Fetch cycle c. Both a and b d. None of these

Description : The act of acquiring an instruction is referred as the____ the instruction: a. Fetching b. Fetch cycle c. Both a and b d. None of these

Last Answer : a. Fetching

Which is the main function of the computer. a. Execute of programs b. Execution of programs c. Both d. None of these

Description : Which is the main function of the computer. a. Execute of programs b. Execution of programs c. Both d. None of these

Last Answer : b. Execution of programs

Assembler works to convert assembly language program into machine language : a. Before the computer can execute it b. After the computer can execute it c. In between execution d. All of these

Description : Assembler works to convert assembly language program into machine language : a. Before the computer can execute it b. After the computer can execute it c. In between execution d. All of these

Last Answer : a. Before the computer can execute it

What is the purpose of microinstruction executions. a. Generate a control signal b. Generate a control signal to compile c. Generate a control signal to execute d. Allof these

Description : What is the purpose of microinstruction executions. a. Generate a control signal b. Generate a control signal to compile c. Generate a control signal to execute d. Allof these

Last Answer : c. Generate a control signal to execute

statement block is executed atleast once for any value of the condition. a. For statement b. Do-while statement c. While statement d. None of these

Description : statement block is executed atleast once for any value of the condition. a. For statement b. Do-while statement c. While statement d. None of these

Last Answer : b. Do-while statement

_is sequence of instructions is executed and repeated any no. of times in loop until logical condition is true: a. Iteration b. Repetition c Botha&b d. None of these

Description : _is sequence of instructions is executed and repeated any no. of times in loop until logical condition is true: a. Iteration b. Repetition c Botha&b d. None of these

Last Answer : c Botha&b

When a subroutine is the parameters are loaded onto the stack and SCAL is executed: a. Executed b. Invoked c. Ended d. = Started

Description : When a subroutine is the parameters are loaded onto the stack and SCAL is executed: a. Executed b. Invoked c. Ended d. = Started

Last Answer : b. Invoked

getchar :: IO char in this given function what is indicated by IO char: a. when getchar is invoked it returns a character b. when getchar is executed it returns a character c. botha & b d. none of these

Description : getchar :: IO char in this given function what is indicated by IO char: a. when getchar is invoked it returns a character b. when getchar is executed it returns a character c. botha & b d. none of these

Last Answer : a. when getchar is invoked it returns a character

What are 2 advantages of cache memory: a. Reduction of average access time for CPU memory b. Reduction of bandwidth of available memory of CPU c. Botha&b d. None of these

Description : What are 2 advantages of cache memory: a. Reduction of average access time for CPU memory b. Reduction of bandwidth of available memory of CPU c. Botha&b d. None of these

Last Answer : c. Botha&b

Which section is basically a sequence of instruction with a clear indication of beginning and end for updating shared variables. a. Racing section b. Critical section c. d. Both None of thes

Description : Which section is basically a sequence of instruction with a clear indication of beginning and end for updating shared variables. a. Racing section b. Critical section c. d. Both None of thes

Last Answer : . Critical sectio

Two important fields of an instruction are. a. Opcode b. Operand c. Only a d. Botha&b

Description : Two important fields of an instruction are. a. Opcode b. Operand c. Only a d. Botha&b

Last Answer : d. Botha&b

The complete set of op-codes for a particular microprocessor defines the_ set for that processor: a. Code b. Function c. Module d. Instruction

Description : The complete set of op-codes for a particular microprocessor defines the_ set for that processor: a. Code b. Function c. Module d. Instruction

Last Answer : d. Instruction

Which is the method by which instructions are selected for execution: a. Instruction selection b. — Selection control c. Instraction sequencing d. All of these

Description : Which is the method by which instructions are selected for execution: a. Instruction selection b. — Selection control c. Instraction sequencing d. All of these

Last Answer : c. Instraction sequencing

The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these

Description : The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these

Last Answer : a. The address of next instruction to be run

As the instruction length increases ————_ of instruction addresses in all the instruction is_ a. Implicit inclusion b. Implicit and disadvantageous c. Explicit and disadvantageous d. Explicit and disadvantageous

Description : As the instruction length increases ————_ of instruction addresses in all the instruction is_ a. Implicit inclusion b. Implicit and disadvantageous c. Explicit and disadvantageous d. Explicit and disadvantageous

Last Answer : c. Explicit and disadvantageous

The contents of the program counter isthe __——__—oof the instruction to be run. a. Data b. Address c. Counter d. None of these

Description : The contents of the program counter isthe __——__—oof the instruction to be run. a. Data b. Address c. Counter d. None of these

Last Answer : b. Address

The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, incremented and next b. Instruction register, incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next

Description : The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, ... incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next

Last Answer : c. Instruction register, incremented and next

Execution of instruction specified by instruction to perform: a. Operation b. Operands c. Both a &b d. None of these

Description : Execution of instruction specified by instruction to perform: a. Operation b. Operands c. Both a &b d. None of these

Last Answer : a. Operation