Description : Loop unrolling is a code optimization technique: (A) that avoids tests at every iteration of the loop (B) that improves performance by decreasing the number of instructions in a basic block. ... loops with outer loops (D) that reorders operations to allow multiple computations to happen in parallel.
Last Answer : (A) that avoids tests at every iteration of the loop
Description : Distinguish pipelining from parallelism?
Last Answer : In computing, a pipeline is a set of data processing elements connected in series, where the output of one element is the input of other. Pipelining is a form of parallelism. Parallelism is simply, multiple operations happening at same time
Description : Data which improves the performance and accessibility of the database are called: (A) Indexes (B) User Data (C) Application Metadata (D) Data Dictionary
Last Answer : (A) Indexes
Description : Internal auditing can affect the scope of the external auditor's audit of financial statements by a. Decreasing the external auditor's need to perform detailed tests b. Eliminating the need ... direct testing by the external auditor to management assertions not directly tested by internal auditing.
Last Answer : Decreasing the external auditor's need to perform detailed tests
Description : What is Instruction Level Parallelism?
Last Answer : Pipelining is used to overlap the execution of instructions and improve performance. This potential overlap among instructions is called instruction level parallelism (ILP).
Description : Adaptive maintenance is a maintenance which ............. (A) Correct errors that were not discovered till testing phase. (B) is carried out to port the existing software to a new environment. (C) improves the system performance. (D) both (B) and (C)
Last Answer : (B) is carried out to port the existing software to a new environment.
Description : The fetch-execute cycle is to use a system know as: a. Assembly line b. Pipelining c. Cache d. None of these
Last Answer : b. Pipelining
Description : In cache memory miss rate indicates. a. Availability of requested data b. Availability of requested address c. Non-Availability of requested data d. Non-Availability of requested address
Last Answer : c. Non-Availability of requested data
Description : Which of the following is not valid with reference to Message Passing Interface (MPI)? (A) MPI can run on any hardware platform (B) The programming model is a distributed memory model. (C) All ... implicit. (D) MPI - Comm - Size returns the total number of MPI processes in specified communication.
Last Answer : (C) All parallelism is implicit.
Description : Relational database schema normalization is NOT for: (A) reducing the number of joins required to satisfy a query. (B) eliminating uncontrolled redundancy of data stored in the database. (C) ... could otherwise occur with inserts and deletes. (D) ensuring that functional dependencies are enforced.
Last Answer : reducing the number of joins required to satisfy a query.
Description : Pipelining strategy is called implement a. instruction execution b. instruction prefetch c. instruction decoding d. instruction manipulation
Last Answer : b. instruction prefetch
Description : Which of the following processor architecture supports easier instruction pipelining? A. Harvard B. Von Neumann C. Both of them D. None of these
Last Answer : A. Harvard
Description : The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use memory bus. A memory read/write employs one machine cycle. For ... (A) 500 Kbytes/sec (B) 2.2 Mbytes/sec (C) 125 Kbytes/sec (D) 250 Kbytes/sec
Last Answer : (D) 250 Kbytes/sec
Description : Computer programs are written in a high level programming language, however, the human readable version of a program is called a) cache b) instruction set c) source code d) word size
Last Answer : c) source code
Description : When cache process starts hit and miss rate defines in cache directory: a. during search reads b. during search writes c. during replace writes d. during finding writes
Last Answer : a. during search reads
Description : ............. is the time required to move the disk arm to the required track. A) Seek time B) Rotational delay C) Latency time D) Access time
Last Answer : A) Seek time
Description : Copy of instruction in cache memory is known as: a Execution cache b. Data cache c. Instruction cache d. Allof these
Last Answer : c. Instruction cache
Description : )Which of the following is NOT one of the primary needs for good project scheduling? 1. Cutting costs and reducing time 2. Decreasing the time required for decision making 3. Eliminating idle time 4. Developing better trouble shooting procedures.
Last Answer : 4. Developing better trouble shooting procedures.
Description : How does randomized hill-climbing choose the next move each time? (A) It generates a random move from the moveset, and accepts this move. (B) It generates a random move from the whole state ... move from the whole state space, and accepts this move only if this move improves the evaluation function.
Last Answer : (C) It generates a random move from the moveset, and accepts this move only if this move improves the evaluation function.
Description : Software safety is a ................... activity that focuses on the identification and assessment of potential hazards that may affect software negatively and cause an entire ... monitoring and management (B) Software quality assurance (C) Software cost estimation (D) Defect removal efficiency
Last Answer : (B) Software quality assurance
Description : ............... is a process model that removes defects before they can precipitate serious hazards. (A) Incremental model (B) Spiral model (C) Cleanroom software engineering (D) Agile model
Last Answer : (C) Cleanroom software engineering
Description : Software safety is quality assurance activity that focuses on hazards that (A) affect the reliability of a software component (B) may cause an entire system to fail. (C) may result from user input errors. (D) prevent profitable marketing of the final product
Last Answer : (B) may cause an entire system to fail.
Description : Interrupt which arises from illegal or erroneous use of an instruction or data is (A) Software interrupt (B) Internal interrupt (C) External interrupt (D) All of the above
Last Answer : (B) Internal interrupt
Description : Translation Look-aside Buffer(TLB) is (A) a cache-memory in which item to be searched is compared one-by-one with the keys. (B) a cache-memory in which item to be searched is compared with ... keys. (D) an associative memory in which item to be searched is compared with all the keys simultaneously.
Last Answer : (D) an associative memory in which item to be searched is compared with all the keys simultaneously.
Description : The virtual address generated by a CPU is 32 bits. The Translation Lookaside Buffer (TLB) can hold total 64 page table entries and a 4-way set associative (i.e. with 4- cache lines in the set). The page size is 4 KB. The minimum size of TLB tag is (A) 12 bits (B) 15 bits (C) 16 bits (D) 20 bits
Last Answer : (C) 16 bits Explanation: VirtualAddress = 32 bits PageSize = 4KB = 12 bits therefore : VPNTag = 20 bits, OffsetTag = 12 bits TLBEntryLength = VPNTag = 20 bits TotalTLBEntries = 64, 4-way implies ... therefore : TLBIndex = 4 bits TLBTag = TLBEntryLength - TLBIndex = 20 - 4 = 16 bits
Description : The directory can be viewed as .................... that translates filenames into their directory entries. (A) Symbol table (B) Partition (C) Swap space (D) Cache
Last Answer : (A) Symbol table
Description : Function of memory management unit is : (A) Address translation (B) Memory allocation (C) Cache management (D) All of the above
Last Answer : Answer: A
Description : In ............. method, the word is written to the block in both the cache and main memory, in parallel. (A) Write through (B) Write back (C) Write protected (D) Direct mapping
Last Answer : (A) Write through
Description : Which of the following is/are hard disk performance parameter? A. Seek time B. Latency period C. Access time D. All of the above
Last Answer : D. All of the above
Description : Define Cache Miss?
Last Answer : A request for data from the cache that cannot be filled because the data is not present in the cache. The control unit must detect a miss and process the miss by fetching the requested data from memory.
Description : The right level of parallelism for maps seems to be around _________ maps per- node. a) 1-10 b) 10-100 c) 100-150 d) 150-200
Last Answer : 10-100
Description : Consider the following justifications for commonly using the two-level CPU scheduling : I. It is used when memory is too small to hold all the ready processes. II. Because its performance is same as that of the FIFO. III. Because it ... ? (A) I, III and IV (B) I and II (C) III and IV (D) I and III
Last Answer : (D) I and III
Description : What is the role of virtualization in cloud computing? A. It removes operating system inefficiencies. B. It improves the performance of web applications. C. It optimizes the utilization of ... . It adds extra load to the underlying physical infrastructure and has no role in cloud computing.
Last Answer : It adds extra load to the underlying physical infrastructure and has no role in cloud computing.
Description : What is the role of virtualization in cloud computing? A. It removes operating system inefficiencies. B. It improves the performance of web applications. C. It optimizes the utilization of ... . It adds extra load to the underlying physical infrastructure and has no role in cloud computing
Description : The following are the characteristics of Positive Stress A. It improves performance B. It feels exciting C. It motivates D. All of the above
Description : The introduction of interpoles in between the main pole improves the performance of d.c. machines, because (A) The interpole produces additional flux to augment the developed torque. (B) The flux waveform is ... armature is removed. (D) A counter e.m.f. is induced in the coil undergoing commutation.
Last Answer : Ans: D Counter e.m.f is produced, it neutralizes the reactive emf.
Description : _____ conflict supports the goals of the group and improves its performance. (a) Formal ; (b) Informal ; (c) Functional ; (d) Dysfunctional
Last Answer : (c) Functional ;
Description : The introduction of interpoles in between the main poles improves the performance of DC machines because: (A) the interpole produces additional flux to augment the torque developed (B) the flux waveform ... of the armature is removed (D) a counter emf is induced in the coil undergoing commutation
Last Answer : The introduction of interpoles in between the main poles improves the performance of DC machines because: a counter emf is induced in the coil undergoing commutation
Description : The performance of data communications network depends on .............. A) Number of users B) The hardware and software C) The transmission D) All of the above
Last Answer : D) All of the above
Description : OOP features are i) Increasing productivity ii) Reusability iii) Decreasing maintenance cost iv) High vulnerability A) 1,2 & 4 B) 1,2 & 3
Last Answer : B) 1,2 & 3
Description : Consider a disk queue with I/O requests on the following cylinders in their arriving order: 6,10,12,54,97,73,128,15,44,110,34,45 The disk head is assumed to be at cylinder 23 and moving in the direction ... . The disk head movement using SCAN-scheduling algorithm is: (1) 172 (2) 173 (3) 227 (4) 228
Last Answer : (2) 173
Description : Which of the following is allowed in a C Arithmetic Instruction? A) [ ] B) { } C) ( ) D) None of the above
Last Answer : C) ( )
Description : CAI stands for ................ A) Computer Aided Instruction B) Computer Aided information C) Cost Added Information D) Computer Aided Infrastructure
Last Answer : B) Computer Aided information
Description : Which is not a typical program control instruction? (A) BR (B) JMP (C) SHL (D) TST
Last Answer : (C) SHL
Description : Computers can have instruction formats with (A) only two address and three address instructions (B) only one address and two address instructions (C) only one address, two address and three address instructions (D) zero address, one address, two address and three address instructions
Last Answer : (D) zero address, one address, two address and three address instructions
Description : A byte addressable computer has a memory capacity of 2 m Kbytes and can perform 2 n operations. An instruction involving 3 operands and one operator needs a maximum of (A) 3m bits (B) m + n bits (C) 3m + n bits (D) 3m + n + 30 bits
Last Answer : (D) 3m + n + 30 bits
Description : The advantage of ............... is that it can reference memory without paying the price of having a full memory address in the instruction. (A) Direct addressing (B) Indexed addressing (C) Register addressing (D) Register Indirect addressing
Last Answer : (D) Register Indirect addressing
Description : The RST 7 instruction in 8085 microprocessor is equivalent to: (A) CALL 0010 H (B) CALL 0034 H (C) CALL 0038 H (D) CALL 003C H
Last Answer : (C) CALL 0038 H
Description : A CPU handles interrupt by executing interrupt service subroutine................. (A) by checking interrupt register after execution of each instruction (B) by checking interrupt register ... cycle (C) whenever an interrupt is registered (D) by checking interrupt register at regular time interval
Last Answer : (A) by checking interrupt register after execution of each instruction
Description : System calls are usually invoked by using: (A) A privileged instruction (B) An indirect jump (C) A software interrupt (D) Polling
Last Answer : (C) A software interrupt