Computers can have instruction formats with (A) only two address and three address instructions (B) only one address and two address instructions (C) only one address, two address and three address instructions (D) zero address, one address, two address and three address instructions

Computers can have instruction formats with (A) only two address and three address instructions (B) only one address and two address instructions (C) only one address, two address and three address instructions (D) zero address, one address, two address and three address instructions
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(D) zero address, one address, two address and three address instructions 
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Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU

Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU

Last Answer : b. Main memory

Suppose that the number of instructions executed between page faults is directly proportional to the number of page frames allocated to a program. If the available memory is doubled, the mean interval between page faults is also doubled. Further, consider that a normal instruction takes one micro second, but if a page fault occurs, it takes 2001 micro seconds. If a program takes 60 sec to run, during which time it gets 15000 page faults, how long would it take to run if twice as much memory were available? (A) 60 sec (B) 30 sec (C) 45 sec (D) 10 sec

Description : Suppose that the number of instructions executed between page faults is directly proportional to the number of page frames allocated to a program. If the available memory is doubled, the mean interval between page faults is also ... memory were available? (A) 60 sec (B) 30 sec (C) 45 sec (D) 10 sec

Last Answer : Answer: C Explanation: T = Ninstr x 1µs + 15,000 x 2,000 µs = 60s Ninstr x 1µs = 60,000,000 µs - 30,000,000 µs = 30,000,000 µs Ninstr = 30,000,000 The number of instruction ... doesn't mean that the program runs twice as fast as on the first system. Here, the performance increase is of 25%.

The advantage of ............... is that it can reference memory without paying the price of having a full memory address in the instruction. (A) Direct addressing (B) Indexed addressing (C) Register addressing (D) Register Indirect addressing

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Last Answer : (D) Register Indirect addressing

When a subroutine is called, the address of the instruction following the CALL instructions stored in/on the a. stack pointer b. accumulator c. program counter d. stack

Description : When a subroutine is called, the address of the instruction following the CALL instructions stored in/on the a. stack pointer b. accumulator c. program counter d. stack

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Description : Write the general formats for file opening and file closing commands?

Last Answer : Ans: For Opening:- fp=fopen(“filename” , “mode”); where ‘fp’ refers to the file pointer. ‘filename’ refers to the name of the file to be opened. ‘mode’ refers to the mode of accessing data. For Closing:- fclose(fp); where fp denotes the file pointer.

In distributed databases, location transparency allows for database users, programmers and administrators to treat the data as if it is at one location. A SQL query with location transparency needs to specify: (A) Inheritances (B) Fragments (C) Locations (D) Local formats

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Last Answer : (B) Fragments

Explain the different instruction formats with examples

Description : Explain the different instruction formats with examples

Last Answer : The instruction set is grouped into the following formats • One byte instruction MOV C,A • Two byte instruction MVI A,39H • Three byte instruction JMP 2345H

In instruction formats instruction is represent by a___ _ of bits: a. Sequence b. Parallel c. Both d. None

Description : In instruction formats instruction is represent by a___ _ of bits: a. Sequence b. Parallel c. Both d. None

Last Answer : a. Sequence

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Description : IPv4 and IPv6 are addresses used to identify computers on the internet. Find the correct statement out of the following: (A) Number of bits required for IPv4 address is more than number of bits required for ... of bits required for IPv6 address. (D) Number of bits required for IPv4 address is 64. 

Last Answer : (C) Number of bits required for IPv4 address is less than number of bits required for IPv6 address.

Which of the following statements concerning Object-Oriented databases is FALSE? (A) Objects in an object-oriented database contain not only data but also methods for processing the data. (B) Object-oriented databases store computational instructions in the same place as the data. (C) Object-oriented databases are more adapt at handling structures (analytical) data than relational databases. (D) Object-oriented databases store more types of data than relational databases and access that data faster.

Description : Which of the following statements concerning Object-Oriented databases is FALSE? (A) Objects in an object-oriented database contain not only data but also methods for processing the data. (B ... Object-oriented databases store more types of data than relational databases and access that data faster.

Last Answer : (C) Object-oriented databases are more adapt at handling structures (analytical) data than relational databases.

When configuring the subnet mask for an IP address, which formats can be used? * dotted-decimal. * Hexadecimal * Bit-count * Octal * Binary

Description : When configuring the subnet mask for an IP address, which formats can be used? * dotted-decimal. * Hexadecimal * Bit-count * Octal * Binary

Last Answer : Correct answer: A, B &C

.......... is a special type of programming language used to provide instructions to the monitor simple batch processing schema. A) Job control language (JCL) B) Processing control language (PCL) C) Batch control language (BCL)

Description : .......... is a special type of programming language used to provide instructions to the monitor simple batch processing schema. A) Job control language (JCL) B) Processing control language (PCL) C) Batch control language (BCL)

Last Answer : A) Job control language (JCL)

A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer? (A) 0.06% (B) 0.12% (C) 1.2% (D) 2.5%

Description : A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average ... of the DMA transfer? (A) 0.06% (B) 0.12% (C) 1.2% (D) 2.5%

Last Answer : Answer: B

What will be the hexadecimal value in the register ax (32-bit) after executing the following instructions? Mov al, 15 Mov ah, 15 Xor al, al Mov cl, 3 Shr ax, cl Codes: (A) 0F00 h (B) 0F0F h (C) 01E0 h (D) FFFF h

Description : What will be the hexadecimal value in the register ax (32-bit) after executing the following instructions? Mov al, 15 Mov ah, 15 Xor al, al Mov cl, 3 Shr ax, cl Codes: (A) 0F00 h (B) 0F0F h (C) 01E0 h (D) FFFF h

Last Answer : (C) 01E0 h

Loop unrolling is a code optimization technique: (A) that avoids tests at every iteration of the loop (B) that improves performance by decreasing the number of instructions in a basic block. (C) that exchanges inner loops with outer loops (D) that reorders operations to allow multiple computations to happen in parallel.

Description : Loop unrolling is a code optimization technique: (A) that avoids tests at every iteration of the loop (B) that improves performance by decreasing the number of instructions in a basic block. ... loops with outer loops (D) that reorders operations to allow multiple computations to happen in parallel.

Last Answer : (A) that avoids tests at every iteration of the loop

Which of the following is allowed in a C Arithmetic Instruction? A) [ ] B) { } C) ( ) D) None of the above

Description : Which of the following is allowed in a C Arithmetic Instruction? A) [ ] B) { } C) ( ) D) None of the above

Last Answer : C) ( )

CAI stands for ................ A) Computer Aided Instruction B) Computer Aided information C) Cost Added Information D) Computer Aided Infrastructure

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Last Answer : B) Computer Aided information

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Description : Interrupt which arises from illegal or erroneous use of an instruction or data is (A) Software interrupt (B) Internal interrupt (C) External interrupt (D) All of the above

Last Answer : (B) Internal interrupt

Which is not a typical program control instruction? (A) BR (B) JMP (C) SHL (D) TST

Description : Which is not a typical program control instruction? (A) BR (B) JMP (C) SHL (D) TST

Last Answer : (C) SHL

A byte addressable computer has a memory capacity of 2 m Kbytes and can perform 2 n operations. An instruction involving 3 operands and one operator needs a maximum of (A) 3m bits (B) m + n bits (C) 3m + n bits (D) 3m + n + 30 bits

Description : A byte addressable computer has a memory capacity of 2 m Kbytes and can perform 2 n operations. An instruction involving 3 operands and one operator needs a maximum of (A) 3m bits (B) m + n bits (C) 3m + n bits (D) 3m + n + 30 bits

Last Answer : (D) 3m + n + 30 bits

The RST 7 instruction in 8085 microprocessor is equivalent to: (A) CALL 0010 H (B) CALL 0034 H (C) CALL 0038 H (D) CALL 003C H

Description : The RST 7 instruction in 8085 microprocessor is equivalent to: (A) CALL 0010 H (B) CALL 0034 H (C) CALL 0038 H (D) CALL 003C H

Last Answer : (C) CALL 0038 H

A CPU handles interrupt by executing interrupt service subroutine................. (A) by checking interrupt register after execution of each instruction (B) by checking interrupt register at the end of the fetch cycle (C) whenever an interrupt is registered (D) by checking interrupt register at regular time interval

Description : A CPU handles interrupt by executing interrupt service subroutine................. (A) by checking interrupt register after execution of each instruction (B) by checking interrupt register ... cycle (C) whenever an interrupt is registered (D) by checking interrupt register at regular time interval

Last Answer : (A) by checking interrupt register after execution of each instruction

System calls are usually invoked by using: (A) A privileged instruction (B) An indirect jump (C) A software interrupt (D) Polling

Description : System calls are usually invoked by using: (A) A privileged instruction (B) An indirect jump (C) A software interrupt (D) Polling

Last Answer : (C) A software interrupt

The ............... addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction. (A) Base indexed (B) Base indexed plus displacement (C) Indexed (D) Displacement

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Last Answer : (D) Displacement

Pipelining improves performance by: (A) decreasing instruction latency (B) eliminating data hazards (C) exploiting instruction level parallelism (D) decreasing the cache miss rate

Description : Pipelining improves performance by: (A) decreasing instruction latency (B) eliminating data hazards (C) exploiting instruction level parallelism (D) decreasing the cache miss rate

Last Answer : (C) exploiting instruction level parallelism

The contents of Register (BL) and Register (AL) of 8085 microprocessor are 49H and 3AH respectively. The contents of AL, the status of carry flag (CF) and sign flag (SF) after executing 'SUB AL, BL' assembly language instruction, are (1) AL=0FH; CF=1; SF=1 (2) AL=F0H; CF=0; SF=0 (3) AL=F1H; CF=1; SF=1 (4) AL=1FH; CF=1; SF=1

Description : The contents of Register (BL) and Register (AL) of 8085 microprocessor are 49H and 3AH respectively. The contents of AL, the status of carry flag (CF) and sign flag (SF) after executing 'SUB AL, BL' assembly language instruction, are ( ... ; CF=0; SF=0 (3) AL=F1H; CF=1; SF=1 (4) AL=1FH; CF=1; SF=1

Last Answer : Answer: 3

The simultaneous execution of two or more instructions is called- 1) Sequential Access 2) Reduced Instruction set computing 3) Multiprocessing 4) None of these

Description : The simultaneous execution of two or more instructions is called- 1) Sequential Access 2) Reduced Instruction set computing 3) Multiprocessing 4) None of these

Last Answer : 3) Multiprocessing

Each coded instruction in a set of instructions is called as…… a.Words b.Alphabet c.Numbers d.Format

Description : Each coded instruction in a set of instructions is called as…… a.Words b.Alphabet c.Numbers d.Format

Last Answer : a.Words

Which is the method by which instructions are selected for execution: a. Instruction selection b. — Selection control c. Instraction sequencing d. All of these

Description : Which is the method by which instructions are selected for execution: a. Instruction selection b. — Selection control c. Instraction sequencing d. All of these

Last Answer : c. Instraction sequencing

Each instruction is executed by set of micro operations termed as. a. Micro instructions b. Mini instructions c. Botha &b d. None of these

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Last Answer : a. Micro instructions

Decoding of an instruction in RISC architecture means decision on working of control unit for: a. Remainder of instructions b. _ Divisor of instructions c. Dividend of instructions d. None of these

Description : Decoding of an instruction in RISC architecture means decision on working of control unit for: a. Remainder of instructions b. _ Divisor of instructions c. Dividend of instructions d. None of these

Last Answer : a. Remainder

Which is data manipulation types are. a. Arithmetic instruction b. Shift instruction c. Logical and bit manipulation instructions d. All of these

Description : Which is data manipulation types are. a. Arithmetic instruction b. Shift instruction c. Logical and bit manipulation instructions d. All of these

Last Answer : d. All of these

The Supdt may prescribe the use, in any Head or Sub office of a beat instruction register ______ for the purpose of communication addressees instructions to the postman a) M 32 b) M 34 c) M 28 d) None of these

Description : The Supdt may prescribe the use, in any Head or Sub office of a beat instruction register ______ for the purpose of communication addressees instructions to the postman a) M 32 b) M 34 c) M 28 d) None of these

Last Answer : a) M 32

Which of the following instruction is of logical instructions? i) CPL A ii) JC rel iii) DA A iv) ANL A, Rn v) RR A vi) CPL bit a) i, v b) v, iii, I c) iv, ii d) v, iii, ii

Description : Which of the following instruction is of logical instructions? i) CPL A ii) JC rel iii) DA A iv) ANL A, Rn v) RR A vi) CPL bit a) i, v b) v, iii, I c) iv, ii d) v, iii, ii

Last Answer : c) iv, i

Which of the following is true about CISC processors? A. The instruction set is non-orthogonal B. The number of general purpose registers is limited C. Instructions are like macros in c language D. Variable length instructions E. All of these F. None of these

Description : Which of the following is true about CISC processors? A. The instruction set is non-orthogonal B. The number of general purpose registers is limited C. Instructions are like macros in c language D. Variable length instructions E. All of these F. None of these

Last Answer : E. All of these 

The three outputs x1x2x3 from the 8x3 priority encoder are used to provide a vector address of the form 101x1x2x300. What is the second highest priority vector address in hexadecimal if the vector addresses are starting from the one with the highest priority? (A) BC (B) A4 (C) BD (D) AC

Description : The three outputs x1x2x3 from the 8x3 priority encoder are used to provide a vector address of the form 101x1x2x300. What is the second highest priority vector address in hexadecimal if the vector addresses are starting from the one with the highest priority? (A) BC (B) A4 (C) BD (D) AC

Last Answer : Answer: B

A three dimensional array in ‘C’ is declared as int A[x][y][z]. Here, the address of an item at the location A[p][q][r] can be computed as follows (where w is the word length of an integer): (A) &A[0][0][0]+w(y*z*q+z*p+r) (B) &A[0][0][0]+w(y*z*p+z*q+r) (C) &A[0][0][0]+w(x*y*p+z*q+r) (D) &A[0][0][0]+w(x*y*q+z*p+r)

Description : A three dimensional array in C' is declared as int A[x][y][z]. Here, the address of an item at the location A[p][q][r] can be computed as follows (where w is the word length of an integer): (A) &A[0][0][0]+w(y*z*q+z*p+r) (B) &A ... *q+r) (C) &A[0][0][0]+w(x*y*p+z*q+r) (D) &A[0][0][0]+w(x*y*q+z*p+r)

Last Answer : Answer: B

Give any three uses of computers in a school library.

Description : Give any three uses of computers in a school library.

Last Answer :  Access to information and primary information sources.  Network accessibility on Intranet and Internet.  User-friendly interface.  Advanced search and retrieval.  Multiple access / Universal accessibility.  Integration with other digital libraries. 

Which of the following characteristics of constructor are true. i) They should be declared in the public section. ii) They are invoked automatically when the objects are created. iii) They do not have return type and void also. iv) We cannot refer their address. v) Constructors cannot virtual. A) Only i, ii, iii and v B) Only ii, iii, iv, and v C) Only i, iii, iv and v D) All i, ii, iii, iv and v

Description : Which of the following characteristics of constructor are true. i) They should be declared in the public section. ii) They are invoked automatically when the objects are created. iii) They do not have return type and void also. ... and v C) Only i, iii, iv and v D) All i, ii, iii, iv and v

Last Answer : D) All i, ii, iii, iv and v

Which of the following condition is true for an object used as a function argument. i) A copy of the entire objects is passed to the function. ii) Only the address of the object is transferred to the function. A) Only i B) Only ii C) Both i and ii D) None of them

Description : Which of the following condition is true for an object used as a function argument. i) A copy of the entire objects is passed to the function. ii) Only the address of the object is transferred to the function. A) Only i B) Only ii C) Both i and ii D) None of them

Last Answer : C) Both i and ii

A .................... architecture assigns only a few essential functions to the kernel, including address spaces, Inter process communication(IPC) and basic scheduling. A) Monolithic kernel B) Micro kernel C) Macro kernel D) Mini kernel

Description : A .................... architecture assigns only a few essential functions to the kernel, including address spaces, Inter process communication(IPC) and basic scheduling. A) Monolithic kernel B) Micro kernel C) Macro kernel D) Mini kernel

Last Answer : B) Micro kernel

In packet-filtering router, the following information can be external from the packet header. i) Source IP address ii) Destination IP address iii) TCP/UDP source port iv) ICMP message type v) TCP/UDP destination port A) i, ii, iii and iv only B) i, iii, iv and v only C) ii, iii, iv and v only D) All i, ii, iii, iv and v

Description : In packet-filtering router, the following information can be external from the packet header. i) Source IP address ii) Destination IP address iii) TCP/UDP source port iv) ICMP message type v) TCP/UDP destination port A) i, ii ... and v only C) ii, iii, iv and v only D) All i, ii, iii, iv and v

Last Answer : D) All i, ii, iii, iv and v

The following protocols and system are commonly used to provide various degrees of security services in computer network. i) IP filtering ii) Reverse Address Translation iii) IP security Architecture (IPsec) iv) Firewalls v) Socks A) i, ii, iii and iv only B) i, iii, iv and v only C) ii, iii, iv and v only D) All i, ii, iii, iv and v

Description : The following protocols and system are commonly used to provide various degrees of security services in computer network. i) IP filtering ii) Reverse Address Translation iii) IP security Architecture (IPsec) iv) Firewalls v) Socks ... only C) ii, iii, iv and v only D) All i, ii, iii, iv and v

Last Answer : B) i, iii, iv and v only

The most important and common protocols associated TCP/IP internetwork layer are. i) Internet protocol(IP) ii) Internet control Message Protocol(ICMP) iii) Bootstrap Protocol (BooTP) iv) Dynamic Host Configuration Protocol (DHCP) v) Address Resolution Protocol (ARP) A) i, ii, iii and iv only B) i, iii, iv and v only C) ii, iii, iv and v only D) All i, ii, iii, iv and v

Description : The most important and common protocols associated TCP/IP internetwork layer are. i) Internet protocol(IP) ii) Internet control Message Protocol(ICMP) iii) Bootstrap Protocol (BooTP) iv) Dynamic Host Configuration Protocol (DHCP) v) ... C) ii, iii, iv and v only D) All i, ii, iii, iv and v

Last Answer : D) All i, ii, iii, iv and v

The most important and common protocols associated TCP/IP internetwork layer are. i) Internet Protocol (IP) ii) Internet Control Message Protocol (ICMP) iii) Bootstrap Protocol (BOOTP) iv) Dynamic Host Configuration Protocol (DHCP) V) Address Resolution Protocol (ARP) A) i, ii, iii, and iv only B) ii, iii, iv and v only C) i, iii, iv and v only D) All i, ii, iii, iv and v only

Description : The most important and common protocols associated TCP/IP internetwork layer are. i) Internet Protocol (IP) ii) Internet Control Message Protocol (ICMP) iii) Bootstrap Protocol (BOOTP) iv) Dynamic Host Configuration Protocol (DHCP) V) ... C) i, iii, iv and v only D) All i, ii, iii, iv and v only

Last Answer : D) All i, ii, iii, iv and v only

Which of the following statement is true? i) An address with all bits 1 is interpreted as all networks or all hosts. ii) The class A network 128.0.0.0 is defined as the loopback network. A) i only B) ii only C) Both A and B D) None of the above

Description : Which of the following statement is true? i) An address with all bits 1 is interpreted as all networks or all hosts. ii) The class A network 128.0.0.0 is defined as the loopback network. A) i only B) ii only C) Both A and B D) None of the above

Last Answer : A) i only

In latest generation computers, the instructions are executed A) Parallel only B) Sequentially only C) Both sequentially and parallel D) All of above

Description : In latest generation computers, the instructions are executed A) Parallel only B) Sequentially only C) Both sequentially and parallel D) All of above

Last Answer : Answer : C

In latest generation computers, the instructions are executed a. Parallel only b. Sequentially only c. Both sequentially and parallel d. All of above

Description : In latest generation computers, the instructions are executed a. Parallel only b. Sequentially only c. Both sequentially and parallel d. All of above

Last Answer : Both sequentially and parallel

In latest generation computers, the instructions are executed a. Parallel only b. Sequentially only c. Both sequentially and parallel d. All of above

Description : In latest generation computers, the instructions are executed a. Parallel only b. Sequentially only c. Both sequentially and parallel d. All of above

Last Answer : c. Both sequentially and parallel