In cache memory miss rate indicates. a. Availability of requested data b. Availability of requested address c. Non-Availability of requested data d. Non-Availability of requested address

In cache memory miss rate indicates.
a. Availability of requested data
b. Availability of requested address
c. Non-Availability of requested data
d. Non-Availability of requested address
by

1 Answer

Answer :

c. Non-Availability of requested data
by

Related questions

In cache memory hit rate indicates. a. Data from requested address is not available b. Data from requested address is available c. Control from requested address is available d. Address from requested address is not available

Description : In cache memory hit rate indicates. a. Data from requested address is not available b. Data from requested address is available c. Control from requested address is available d. Address from requested address is not available

Last Answer : b. Data from requested address is available

Copy of data in cache memory is called. a. Datacache b. Execution cache c. Address cache d. Control cache

Description : Copy of data in cache memory is called. a. Datacache b. Execution cache c. Address cache d. Control cache

Last Answer : a. Datacache

When cache process starts hit and miss rate defines in cache directory: a. during search reads b. during search writes c. during replace writes d. during finding writes

Description : When cache process starts hit and miss rate defines in cache directory: a. during search reads b. during search writes c. during replace writes d. during finding writes

Last Answer : a. during search reads

Which memory is used to copy instructions or data currently used by CPU: a. Main memory b. Secondary memory c. Cache memory d. None of these

Description : Which memory is used to copy instructions or data currently used by CPU: a. Main memory b. Secondary memory c. Cache memory d. None of these

Last Answer : c. Cache memory

Copy of instruction in cache memory is known as: a Execution cache b. Data cache c. Instruction cache d. Allof these

Description : Copy of instruction in cache memory is known as: a Execution cache b. Data cache c. Instruction cache d. Allof these

Last Answer : c. Instruction cache

Updating writes to cache data andalsoto___ a. Directories b. Memory c. Registers d. Folders

Description : Updating writes to cache data andalsoto___ a. Directories b. Memory c. Registers d. Folders

Last Answer : a. Directories

Which memory is assembled between main memory and CPU: a. Primary memory b. Cache memory Cc. Botha & b d. None of these

Description : Which memory is assembled between main memory and CPU: a. Primary memory b. Cache memory Cc. Botha & b d. None of these

Last Answer : b. Cache memory

Which unit acts as the brain of the computer which control other peripherals and interfaces: a. Memory unit b. Cache unit c. Timing and control unit d. None of these

Description : Which unit acts as the brain of the computer which control other peripherals and interfaces: a. Memory unit b. Cache unit c. Timing and control unit d. None of these

Last Answer : c. Timing and control unit

Cache memory is located between main memory and : a. CPU b. Memory c. Botha &b d. None of these

Description : Cache memory is located between main memory and : a. CPU b. Memory c. Botha &b d. None of these

Last Answer : a. CPU

What are 2 advantages of cache memory: a. Reduction of average access time for CPU memory b. Reduction of bandwidth of available memory of CPU c. Botha&b d. None of these

Description : What are 2 advantages of cache memory: a. Reduction of average access time for CPU memory b. Reduction of bandwidth of available memory of CPU c. Botha&b d. None of these

Last Answer : c. Botha&b

On what method search in cache memory used by the system. a. Cache directing b. Cache mapping c. Cache controlling d. Cache invalidation

Description : On what method search in cache memory used by the system. a. Cache directing b. Cache mapping c. Cache controlling d. Cache invalidation

Last Answer : b. Cache mapping

function select takes op code in IR translating to function of ALU and it may be compact binary code or one line per ALU: a ALU b CPU c. Memory d. Cache

Description : function select takes op code in IR translating to function of ALU and it may be compact binary code or one line per ALU: a ALU b CPU c. Memory d. Cache

Last Answer : a ALU

The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read

Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read

Last Answer : d. Address register and read

Which operation puts memory address in memory address register and data in DR. a Memory read b. Memory write c Both d. None

Description : Which operation puts memory address in memory address register and data in DR. a Memory read b. Memory write c Both d. None

Last Answer : b. Memory write

Addresses in control memory is made by for each register group: a. Address select logic b. Data select logic c. Control select logic d. All of these

Description : Addresses in control memory is made by for each register group: a. Address select logic b. Data select logic c. Control select logic d. All of these

Last Answer : a. Address select logic

What type of circuit is used by control memory to interconnect registers. a. Data routing circuit b. Address routing circuit c. Control routing circuit d. None of the these

Description : What type of circuit is used by control memory to interconnect registers. a. Data routing circuit b. Address routing circuit c. Control routing circuit d. None of the these

Last Answer : a. Data routing circuit

Various machine level components are: a. Address register > Program counter c Data register d. Accumulator register e. Memory of 2K,16 bits/word RAM f. Multiplexers g. Allof these

Description : Various machine level components are: a. Address register > Program counter c Data register d. Accumulator register e. Memory of 2K,16 bits/word RAM f. Multiplexers g. Allof these

Last Answer : g. Allof these

Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU

Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU

Last Answer : b. Main memory

Which 3 areas are used by cache process: a. Search, updating, invalidation b. Write, updating, invalidation c. Search, read, updating d. —_Invalidation, updating, requesting

Description : Which 3 areas are used by cache process: a. Search, updating, invalidation b. Write, updating, invalidation c. Search, read, updating d. —_Invalidation, updating, requesting

Last Answer : a. Search, updating, invalidation

Pipelining improves performance by: (A) decreasing instruction latency (B) eliminating data hazards (C) exploiting instruction level parallelism (D) decreasing the cache miss rate

Description : Pipelining improves performance by: (A) decreasing instruction latency (B) eliminating data hazards (C) exploiting instruction level parallelism (D) decreasing the cache miss rate

Last Answer : (C) exploiting instruction level parallelism

The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, incremented and next b. Instruction register, incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next

Description : The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, ... incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next

Last Answer : c. Instruction register, incremented and next

Which is addressed by sign extending the 16-bit displacement to 32-bit: a. Memory address b. Effective memory address c. Both a and b d. None of these

Description : Which is addressed by sign extending the 16-bit displacement to 32-bit: a. Memory address b. Effective memory address c. Both a and b d. None of these

Last Answer : b. Effective memory address

The register that includes the address of the memory unit is termed asthe _ a. MAR b PC Cc. IR d. None of these

Description : The register that includes the address of the memory unit is termed asthe _ a. MAR b PC Cc. IR d. None of these

Last Answer : a. MAR

In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR

Description : In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR

Last Answer : b. CPU

In memory read the operation puts memory address on to a register known as : a. PC b. ALU ce. MAR d. — Allof these

Description : In memory read the operation puts memory address on to a register known as : a. PC b. ALU ce. MAR d. — Allof these

Last Answer : ce. MAR

The memory bus is also referred as _ a. Databus b. Address bus c. Memory bus d. — Allof these

Description : The memory bus is also referred as _ a. Databus b. Address bus c. Memory bus d. — Allof these

Last Answer : a. Databus

___uses the stack to store return address of subroutine: a. CPU b. Microprocessor c. register d. memory

Description : ___uses the stack to store return address of subroutine: a. CPU b. Microprocessor c. register d. memory

Last Answer : b. Microprocessor

Micro-orders generate the_ __ address of operand and execute instruction and prepare for fetching next instruction from the main memory: a. Physical b. Effective c. Logical d. all of above

Description : Micro-orders generate the_ __ address of operand and execute instruction and prepare for fetching next instruction from the main memory: a. Physical b. Effective c. Logical d. all of above

Last Answer : b. Effective

How many modes the address in control memory are divided. a 2 b 3 c. 5 d 7

Description : How many modes the address in control memory are divided. a 2 b 3 c. 5 d 7

Last Answer : a 2

Invalidation writes only to___ and erases previously residing address in memory: a. Folders b. Memory c. Directory d. Files

Description : Invalidation writes only to___ and erases previously residing address in memory: a. Folders b. Memory c. Directory d. Files

Last Answer : c. Directory

In stack organization address register is known as the: a. Memory stack b. Stack pointer c. Push operation d. Pop operation

Description : In stack organization address register is known as the: a. Memory stack b. Stack pointer c. Push operation d. Pop operation

Last Answer : b. Stack pointer

Memory —mapped ___is used this is just another memory address. a. Input b. Output c. Both d. None

Description : Memory —mapped ___is used this is just another memory address. a. Input b. Output c. Both d. None

Last Answer : c. Both

In post-indexing the contents of the address field are used to access a memory location containing a___ address: Immediate addressing Direct addressing Register addressing ao | None of these

Description : In post-indexing the contents of the address field are used to access a memory location containing a___ address: Immediate addressing Direct addressing Register addressing ao | None of these

Last Answer : Direct addressing

When subroutine is called contents of program counter is location address of __ instruction following call instruction is stored on _ __and program execution is transferred to __ address. a. Non executable, pointer and subroutine b. Executable, Stack and Main program Cc. Executable, Queue and Subroutine d. Executable, Stack and Subroutine

Description : When subroutine is called contents of program counter is location address of __ instruction following call instruction is stored on _ __and program execution is transferred to __ address. a. Non ... , Stack and Main program Cc. Executable, Queue and Subroutine d. Executable, Stack and Subroutine

Last Answer : d. Executable, Stack and Subroutine

The contents of the program counter isthe __——__—oof the instruction to be run. a. Data b. Address c. Counter d. None of these

Description : The contents of the program counter isthe __——__—oof the instruction to be run. a. Data b. Address c. Counter d. None of these

Last Answer : b. Address

is a symbolic representation of discrete elements of information: a. Data b. Code c. Address d. Control

Description : is a symbolic representation of discrete elements of information: a. Data b. Code c. Address d. Control

Last Answer : b. Code

For each micro operation the control unit generates set of_ signals. a. Control b. Address c. Data d. None of these

Description : For each micro operation the control unit generates set of_ signals. a. Control b. Address c. Data d. None of these

Last Answer : a. Control

The stack pointer is maintained in a : a. Data b. Register c. Address d. None of these

Description : The stack pointer is maintained in a : a. Data b. Register c. Address d. None of these

Last Answer : b. Register

Which control refers to the track of the address of instructions. a. Data control b. Register control c. Program control d. None of these

Description : Which control refers to the track of the address of instructions. a. Data control b. Register control c. Program control d. None of these

Last Answer : c. Program control

NUMA stands for. a. Number Uniform memory access b. Not Uniform memory access Cc. Non Uniform memory access d. __ Allof these

Description : NUMA stands for. a. Number Uniform memory access b. Not Uniform memory access Cc. Non Uniform memory access d. __ Allof these

Last Answer : a. Number Uniform memory access

Which are benefit of input/output interrupt: a. It is an external analogy to exceptions b. The processor initiates and perform all I/O operation c. The data is transferred into the memory through interrupt handler d. = Alllof these

Description : Which are benefit of input/output interrupt: a. It is an external analogy to exceptions b. The processor initiates and perform all I/O operation c. The data is transferred into the memory through interrupt handler d. = Alllof these

Last Answer : d. = Alllof these

END of macro definition by: a. NAME b. MEND c. DATA d. MEMORY

Description : END of macro definition by: a. NAME b. MEND c. DATA d. MEMORY

Last Answer : b. MEND

Before checking the program for errors in translating code into machine language the high level language code is loaded into __ a. Register b. Memory c. Data d. CPU

Description : Before checking the program for errors in translating code into machine language the high level language code is loaded into __ a. Register b. Memory c. Data d. CPU

Last Answer : b. Memory

Control memory is part of __ that has addressable storage registers and used as temporary storage for data. a. ROM b. RAM c. CPU d. Memory

Description : Control memory is part of __ that has addressable storage registers and used as temporary storage for data. a. ROM b. RAM c. CPU d. Memory

Last Answer : b. RAM

Which functions are performed by CU: a. Data exchange b/w CPU and memory or I/O modules b. External operations c. Internal operations inside CPU d Botha&c

Description : Which functions are performed by CU: a. Data exchange b/w CPU and memory or I/O modules b. External operations c. Internal operations inside CPU d Botha&c

Last Answer : d Botha&c

___is the data paths link CPU registers with memory or I/O modules. a. External data paths b. Internal data paths c. Boreal data paths d. Exchange data paths

Description : ___is the data paths link CPU registers with memory or I/O modules. a. External data paths b. Internal data paths c. Boreal data paths d. Exchange data paths

Last Answer : a. External data paths

The length of instruction set depends on: a. Data size b. Memory size c. Both d. None

Description : The length of instruction set depends on: a. Data size b. Memory size c. Both d. None

Last Answer : b. Memory size

MIMD stands for: a. Multiple input multiple data b. Memory input multiple data c. Multiple instruction multiple data d. Memory instruction multiple data

Description : MIMD stands for: a. Multiple input multiple data b. Memory input multiple data c. Multiple instruction multiple data d. Memory instruction multiple data

Last Answer : c. Multiple instruction multiple data

Which types of register holds a single vector containing at least two read ports and one write ports: a. Data system b. Data base Cc. Memory d. Vector register

Description : Which types of register holds a single vector containing at least two read ports and one write ports: a. Data system b. Data base Cc. Memory d. Vector register

Last Answer : d. Vector register

Parallel computing means doing several takes simultaneously thus improving the performance of the a. Data system b. Computer system Cc. Memory d. Vector register

Description : Parallel computing means doing several takes simultaneously thus improving the performance of the a. Data system b. Computer system Cc. Memory d. Vector register

Last Answer : b. Computer system