Updating writes to cache data andalsoto___ a. Directories b. Memory c. Registers d. Folders

Updating writes to cache data andalsoto___

a. Directories
b. Memory
c. Registers
d. Folders
by

1 Answer

Answer :

a. Directories
by

Related questions

Invalidation writes only to___ and erases previously residing address in memory: a. Folders b. Memory c. Directory d. Files

Description : Invalidation writes only to___ and erases previously residing address in memory: a. Folders b. Memory c. Directory d. Files

Last Answer : c. Directory

Which 3 areas are used by cache process: a. Search, updating, invalidation b. Write, updating, invalidation c. Search, read, updating d. —_Invalidation, updating, requesting

Description : Which 3 areas are used by cache process: a. Search, updating, invalidation b. Write, updating, invalidation c. Search, read, updating d. —_Invalidation, updating, requesting

Last Answer : a. Search, updating, invalidation

When cache process starts hit and miss rate defines in cache directory: a. during search reads b. during search writes c. during replace writes d. during finding writes

Description : When cache process starts hit and miss rate defines in cache directory: a. during search reads b. during search writes c. during replace writes d. during finding writes

Last Answer : a. during search reads

Control memory is part of __ that has addressable storage registers and used as temporary storage for data. a. ROM b. RAM c. CPU d. Memory

Description : Control memory is part of __ that has addressable storage registers and used as temporary storage for data. a. ROM b. RAM c. CPU d. Memory

Last Answer : b. RAM

What type of circuit is used by control memory to interconnect registers. a. Data routing circuit b. Address routing circuit c. Control routing circuit d. None of the these

Description : What type of circuit is used by control memory to interconnect registers. a. Data routing circuit b. Address routing circuit c. Control routing circuit d. None of the these

Last Answer : a. Data routing circuit

___is the data paths link CPU registers with memory or I/O modules. a. External data paths b. Internal data paths c. Boreal data paths d. Exchange data paths

Description : ___is the data paths link CPU registers with memory or I/O modules. a. External data paths b. Internal data paths c. Boreal data paths d. Exchange data paths

Last Answer : a. External data paths

Which memory is used to copy instructions or data currently used by CPU: a. Main memory b. Secondary memory c. Cache memory d. None of these

Description : Which memory is used to copy instructions or data currently used by CPU: a. Main memory b. Secondary memory c. Cache memory d. None of these

Last Answer : c. Cache memory

Copy of instruction in cache memory is known as: a Execution cache b. Data cache c. Instruction cache d. Allof these

Description : Copy of instruction in cache memory is known as: a Execution cache b. Data cache c. Instruction cache d. Allof these

Last Answer : c. Instruction cache

Copy of data in cache memory is called. a. Datacache b. Execution cache c. Address cache d. Control cache

Description : Copy of data in cache memory is called. a. Datacache b. Execution cache c. Address cache d. Control cache

Last Answer : a. Datacache

In cache memory hit rate indicates. a. Data from requested address is not available b. Data from requested address is available c. Control from requested address is available d. Address from requested address is not available

Description : In cache memory hit rate indicates. a. Data from requested address is not available b. Data from requested address is available c. Control from requested address is available d. Address from requested address is not available

Last Answer : b. Data from requested address is available

In cache memory miss rate indicates. a. Availability of requested data b. Availability of requested address c. Non-Availability of requested data d. Non-Availability of requested address

Description : In cache memory miss rate indicates. a. Availability of requested data b. Availability of requested address c. Non-Availability of requested data d. Non-Availability of requested address

Last Answer : c. Non-Availability of requested data

Microcodes are stored as firmware in _ a. Memory chips b. Registers c. accumulators d. none of these

Description : Microcodes are stored as firmware in _ a. Memory chips b. Registers c. accumulators d. none of these

Last Answer : a. Memory chips

Which memory is assembled between main memory and CPU: a. Primary memory b. Cache memory Cc. Botha & b d. None of these

Description : Which memory is assembled between main memory and CPU: a. Primary memory b. Cache memory Cc. Botha & b d. None of these

Last Answer : b. Cache memory

Which unit acts as the brain of the computer which control other peripherals and interfaces: a. Memory unit b. Cache unit c. Timing and control unit d. None of these

Description : Which unit acts as the brain of the computer which control other peripherals and interfaces: a. Memory unit b. Cache unit c. Timing and control unit d. None of these

Last Answer : c. Timing and control unit

Cache memory is located between main memory and : a. CPU b. Memory c. Botha &b d. None of these

Description : Cache memory is located between main memory and : a. CPU b. Memory c. Botha &b d. None of these

Last Answer : a. CPU

What are 2 advantages of cache memory: a. Reduction of average access time for CPU memory b. Reduction of bandwidth of available memory of CPU c. Botha&b d. None of these

Description : What are 2 advantages of cache memory: a. Reduction of average access time for CPU memory b. Reduction of bandwidth of available memory of CPU c. Botha&b d. None of these

Last Answer : c. Botha&b

On what method search in cache memory used by the system. a. Cache directing b. Cache mapping c. Cache controlling d. Cache invalidation

Description : On what method search in cache memory used by the system. a. Cache directing b. Cache mapping c. Cache controlling d. Cache invalidation

Last Answer : b. Cache mapping

function select takes op code in IR translating to function of ALU and it may be compact binary code or one line per ALU: a ALU b CPU c. Memory d. Cache

Description : function select takes op code in IR translating to function of ALU and it may be compact binary code or one line per ALU: a ALU b CPU c. Memory d. Cache

Last Answer : a ALU

Which are internal operations inside CPU: a. Data transfer b/w registers b. Instructing ALU to operate data c. Regulation of other internal operations d. All of these

Description : Which are internal operations inside CPU: a. Data transfer b/w registers b. Instructing ALU to operate data c. Regulation of other internal operations d. All of these

Last Answer : d. All of these

In IT, the method for updating the main memory as soon as a word is removed from the cache is called (1) Write – through (2) Write – back (3) Protected – write (4) Cache – write

Description : In IT, the method for updating the main memory as soon as a word is removed from the cache is called (1) Write – through (2) Write – back (3) Protected – write (4) Cache – write

Last Answer : Write – back

Digital Forensics entails _____. A. Accessing the system's directories viewing mode and navigating through the various systems files and folders B. Undeleting and recovering lost files C. Identifying and solving computer crimes D. The identification, preservation, recovery, restoration and presentation of digital evidence from systems and devices

Description : Digital Forensics entails _____. A. Accessing the system's directories viewing mode and navigating through the various systems files and folders B. Undeleting and recovering lost ... identification, preservation, recovery, restoration and presentation of digital evidence from systems and devices

Last Answer : D. The identification, preservation, recovery, restoration and presentation of digital evidence from systems and devices

Which section is basically a sequence of instruction with a clear indication of beginning and end for updating shared variables. a. Racing section b. Critical section c. d. Both None of thes

Description : Which section is basically a sequence of instruction with a clear indication of beginning and end for updating shared variables. a. Racing section b. Critical section c. d. Both None of thes

Last Answer : . Critical sectio

The front panel display provides lights as green LED represent sand red LED represent _ for device programmer who writes input/output basic: a. Busy and Error b. Error and Busy c. Busy and Busy d. Error and Error

Description : The front panel display provides lights as green LED represent sand red LED represent _ for device programmer who writes input/output basic: a. Busy and Error b. Error and Busy c. Busy and Busy d. Error and Error

Last Answer : a. Busy and Error

You will use _____between main memory & registers to hide "slow" DRAM: a) RAM b) Cache c) ROM d) None of These

Description : You will use _____between main memory & registers to hide "slow" DRAM: a) RAM b) Cache c) ROM d) None of These

Last Answer : RAM

Which of the following correctly lists computer memory types from highest to lowest speed? (A) Secondary Storage: Main Memory (RAM); Cache. Memory; CPU Registers (B) CPU Registers; Cache Memory; Secondary Storage; Main Memory (RAM) (C) CPU Registers; Cache Memory: Main Memory (RAM); Secondary Storage (D) Cache Memory; CPU Registers; Main Memory (RAM); Secondary Storage

Description : Which of the following correctly lists computer memory types from highest to lowest speed? (A) Secondary Storage: Main Memory (RAM); Cache. Memory; CPU Registers (B) CPU Registers; Cache Memory; ... (RAM); Secondary Storage (D) Cache Memory; CPU Registers; Main Memory (RAM); Secondary Storage

Last Answer : Answer: C (CPU Registers > Cache Memory > Main Memory (RAM) > Secondary Storage)

In RISC architecture access to registers is made as a block and register file in a particular register can be selected by using: a. Multiplexer b. Decoder c. Subtractor d. Adder

Description : In RISC architecture access to registers is made as a block and register file in a particular register can be selected by using: a. Multiplexer b. Decoder c. Subtractor d. Adder

Last Answer : b. Decoder

The part of a processor which contains hardware necessary to perform all the operations required by a computer: a) Data path b) Controller c) Registers d) Cache

Description : The part of a processor which contains hardware necessary to perform all the operations required by a computer: a) Data path b) Controller c) Registers d) Cache

Last Answer : Answer: a Explanation: A processor is a part of the computer which does all the data manipulation and decision making. A processor comprises of: A data path which contains the hardware necessary to ... the data path what needs to be done. The registers act as intermediate storage for the data

The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read

Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read

Last Answer : d. Address register and read

Which are benefit of input/output interrupt: a. It is an external analogy to exceptions b. The processor initiates and perform all I/O operation c. The data is transferred into the memory through interrupt handler d. = Alllof these

Description : Which are benefit of input/output interrupt: a. It is an external analogy to exceptions b. The processor initiates and perform all I/O operation c. The data is transferred into the memory through interrupt handler d. = Alllof these

Last Answer : d. = Alllof these

Which operation puts memory address in memory address register and data in DR. a Memory read b. Memory write c Both d. None

Description : Which operation puts memory address in memory address register and data in DR. a Memory read b. Memory write c Both d. None

Last Answer : b. Memory write

END of macro definition by: a. NAME b. MEND c. DATA d. MEMORY

Description : END of macro definition by: a. NAME b. MEND c. DATA d. MEMORY

Last Answer : b. MEND

Before checking the program for errors in translating code into machine language the high level language code is loaded into __ a. Register b. Memory c. Data d. CPU

Description : Before checking the program for errors in translating code into machine language the high level language code is loaded into __ a. Register b. Memory c. Data d. CPU

Last Answer : b. Memory

Addresses in control memory is made by for each register group: a. Address select logic b. Data select logic c. Control select logic d. All of these

Description : Addresses in control memory is made by for each register group: a. Address select logic b. Data select logic c. Control select logic d. All of these

Last Answer : a. Address select logic

Various machine level components are: a. Address register > Program counter c Data register d. Accumulator register e. Memory of 2K,16 bits/word RAM f. Multiplexers g. Allof these

Description : Various machine level components are: a. Address register > Program counter c Data register d. Accumulator register e. Memory of 2K,16 bits/word RAM f. Multiplexers g. Allof these

Last Answer : g. Allof these

Which functions are performed by CU: a. Data exchange b/w CPU and memory or I/O modules b. External operations c. Internal operations inside CPU d Botha&c

Description : Which functions are performed by CU: a. Data exchange b/w CPU and memory or I/O modules b. External operations c. Internal operations inside CPU d Botha&c

Last Answer : d Botha&c

Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU

Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU

Last Answer : b. Main memory

The length of instruction set depends on: a. Data size b. Memory size c. Both d. None

Description : The length of instruction set depends on: a. Data size b. Memory size c. Both d. None

Last Answer : b. Memory size

MIMD stands for: a. Multiple input multiple data b. Memory input multiple data c. Multiple instruction multiple data d. Memory instruction multiple data

Description : MIMD stands for: a. Multiple input multiple data b. Memory input multiple data c. Multiple instruction multiple data d. Memory instruction multiple data

Last Answer : c. Multiple instruction multiple data

Which types of register holds a single vector containing at least two read ports and one write ports: a. Data system b. Data base Cc. Memory d. Vector register

Description : Which types of register holds a single vector containing at least two read ports and one write ports: a. Data system b. Data base Cc. Memory d. Vector register

Last Answer : d. Vector register

Parallel computing means doing several takes simultaneously thus improving the performance of the a. Data system b. Computer system Cc. Memory d. Vector register

Description : Parallel computing means doing several takes simultaneously thus improving the performance of the a. Data system b. Computer system Cc. Memory d. Vector register

Last Answer : b. Computer system

Which of the following statements is not true about disk-arm scheduling algorithms ? (A) SSTF (shortest seek time first) algorithm increases performance of FCFS. (B) The number of requests for disk service are not influenced by file allocation method. (C) Caching the directories and index blocks in main memory can also help in reducing disk arm movements. (D) SCAN and C-SCAN algorithms are less likely to have a starvation problem.

Description : Which of the following statements is not true about disk-arm scheduling algorithms ? (A) SSTF (shortest seek time first) algorithm increases performance of FCFS. (B) The number of requests for disk ... arm movements. (D) SCAN and C-SCAN algorithms are less likely to have a starvation problem.

Last Answer : (B) The number of requests for disk service are not influenced by file allocation method.

emaphore provides mutual exclusion for accesses to the buffer pool and is initialized to the value: a. Mutex b. Mutual Cc. Memory d. __ Allof these

Description : emaphore provides mutual exclusion for accesses to the buffer pool and is initialized to the value: a. Mutex b. Mutual Cc. Memory d. __ Allof these

Last Answer : Mutex

specify where to get the source and destination operands for the operation specified by the a. Operand fields and opcode b. Opcode and operand c. Source and destination d. Cpu and memory

Description : specify where to get the source and destination operands for the operation specified by the a. Operand fields and opcode b. Opcode and operand c. Source and destination d. Cpu and memory

Last Answer : a. Operand fields and opcode

The source/destination of operands can be the_ or one of the general-purpose register: a. Memory b. One c. both d. None of these

Description : The source/destination of operands can be the_ or one of the general-purpose register: a. Memory b. One c. both d. None of these

Last Answer : a. Memory

_is the step during which a new instruction is read from the memory: a Decode b. Fetch c. Execute d. None of these

Description : _is the step during which a new instruction is read from the memory: a Decode b. Fetch c. Execute d. None of these

Last Answer : b. Fetch

The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, incremented and next b. Instruction register, incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next

Description : The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, ... incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next

Last Answer : c. Instruction register, incremented and next

Which unit works as an interface between the processor and all the memories on chip or off- chip: a. Timing unit b. Control unit c. Memory control unit d All of these

Description : Which unit works as an interface between the processor and all the memories on chip or off- chip: a. Timing unit b. Control unit c. Memory control unit d All of these

Last Answer : c. Memory control unit

sis given an instruction in machine language this instruction is fetched from the memory by the CPU to execute: a. ALU b. CPU c. MU d. All of these

Description : sis given an instruction in machine language this instruction is fetched from the memory by the CPU to execute: a. ALU b. CPU c. MU d. All of these

Last Answer : b. CPU

Which instruction are 32 bits long , with extra 16 bits. a. Memory reference instruction b. Memory reference format c. Both d. None of these

Description : Which instruction are 32 bits long , with extra 16 bits. a. Memory reference instruction b. Memory reference format c. Both d. None of these

Last Answer : a. Memory reference instruction

Which is addressed by sign extending the 16-bit displacement to 32-bit: a. Memory address b. Effective memory address c. Both a and b d. None of these

Description : Which is addressed by sign extending the 16-bit displacement to 32-bit: a. Memory address b. Effective memory address c. Both a and b d. None of these

Last Answer : b. Effective memory address