Description : Which instruction are 32 bits long , with extra 16 bits. a. Memory reference instruction b. Memory reference format c. Both d. None of these
Last Answer : a. Memory reference instruction
Description : The _stack can be 4-word memory addressed by 2 bits from an up/down counter known as the stack pointer: a. FIFO b. PIPO c. SISO d. LIFO
Last Answer : d. LIFO
Description : Micro-orders generate the_ __ address of operand and execute instruction and prepare for fetching next instruction from the main memory: a. Physical b. Effective c. Logical d. all of above
Last Answer : b. Effective
Description : Various machine level components are: a. Address register > Program counter c Data register d. Accumulator register e. Memory of 2K,16 bits/word RAM f. Multiplexers g. Allof these
Last Answer : g. Allof these
Description : AOinthesignbitrepresentsa sand. 1 in the sign bit represents a ee a. Positive number b. Negative number c. Both d. None of these
Last Answer : c. Both
Description : Which are the types of important ideas to notice about these odometer readings: a. The MSB is the sign bit .O for a +sign and 1 for a— sign b. The negative number represent the 2’s complement of the positive number c. Both d. __ Allof these
Description : doesn’t need a linker to load it and is loaded _ a. Indirectly b. Directly c. Extending d. None of these
Last Answer : b. Directly
Description : A memory unit stores 2^16 bytes in 32-bit words. How many address bits are necessary in order to retrieve a single word from this memory unit?
Last Answer : Each word is 4 bytes, which occupies 4 consecutive addresses at 16 bits each. The first 14 bits of these addresses will be the same, differing only in the two least significant bits. You only need to specify the first 14 bits, because there are only 2^14 words occupying those 2^16 bytes.
Description : A 32-bit address bus allows access to a memory of capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb 2.Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors
Last Answer : c) all x86 processors
Description : In the case of a right arithmetic shift the sign bit values are shifted to the a. Left b. Right Cc. Up d. Down
Last Answer : a. Left
Description : Which operation puts memory address in memory address register and data in DR. a Memory read b. Memory write c Both d. None
Last Answer : b. Memory write
Description : Memory —mapped ___is used this is just another memory address. a. Input b. Output c. Both d. None
Description : EA stands for. a. Effective add b. Effective absolute c. Effective address d. End address
Last Answer : c. Effective address
Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read
Last Answer : d. Address register and read
Description : The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, ... incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next
Last Answer : c. Instruction register, incremented and next
Description : The register that includes the address of the memory unit is termed asthe _ a. MAR b PC Cc. IR d. None of these
Last Answer : a. MAR
Description : In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR
Last Answer : b. CPU
Description : In memory read the operation puts memory address on to a register known as : a. PC b. ALU ce. MAR d. — Allof these
Last Answer : ce. MAR
Description : The memory bus is also referred as _ a. Databus b. Address bus c. Memory bus d. — Allof these
Last Answer : a. Databus
Description : ___uses the stack to store return address of subroutine: a. CPU b. Microprocessor c. register d. memory
Last Answer : b. Microprocessor
Description : How many modes the address in control memory are divided. a 2 b 3 c. 5 d 7
Last Answer : a 2
Description : Addresses in control memory is made by for each register group: a. Address select logic b. Data select logic c. Control select logic d. All of these
Last Answer : a. Address select logic
Description : What type of circuit is used by control memory to interconnect registers. a. Data routing circuit b. Address routing circuit c. Control routing circuit d. None of the these
Last Answer : a. Data routing circuit
Description : Copy of data in cache memory is called. a. Datacache b. Execution cache c. Address cache d. Control cache
Last Answer : a. Datacache
Description : In cache memory hit rate indicates. a. Data from requested address is not available b. Data from requested address is available c. Control from requested address is available d. Address from requested address is not available
Last Answer : b. Data from requested address is available
Description : In cache memory miss rate indicates. a. Availability of requested data b. Availability of requested address c. Non-Availability of requested data d. Non-Availability of requested address
Last Answer : c. Non-Availability of requested data
Description : Invalidation writes only to___ and erases previously residing address in memory: a. Folders b. Memory c. Directory d. Files
Last Answer : c. Directory
Description : In stack organization address register is known as the: a. Memory stack b. Stack pointer c. Push operation d. Pop operation
Last Answer : b. Stack pointer
Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU
Last Answer : b. Main memory
Description : In post-indexing the contents of the address field are used to access a memory location containing a___ address: Immediate addressing Direct addressing Register addressing ao | None of these
Last Answer : Direct addressing
Description : Which addressing is an extremely influential way of addressing: a. Displacement addressing b. Immediate addressing 9 Direct addressing a Register addressing
Last Answer : a. Displacement addressing
Description : Length of Port address in TCP/IP is A. 8 bit long B. 4 bit long C. 32 bit long D. 16 bit long
Last Answer : D. 16 bit long
Description : What is the size of an IP address? A. 64 bit B. 128 bit C. 16 bit D. 32 bit
Last Answer : D. 32 bit
Description : Length of Port address in TCP/IP is a. 8 bit long b. 4 bit long c. 32 bit long d. 16 bit long
Last Answer : d. 16 bit long
Description : In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices. a) False b) True
Last Answer : True
Description : The number of bit required to express and ___ are determined by the accuracy desired from the computing system . a. Exponent b. Mantissa ce. Both d. None f these
Last Answer : ce. Both
Description : The bit positionina can be numbered from 1 through 2h, a. Hamming code word b. Hamming distance word c. Both d. None of these
Last Answer : a. Hamming code word
Description : A micro operation every bit of a register is a: a. Constant b. Variable c. Both d. None
Last Answer : b. Variable
Description : Which processor provided 1 MB memory: a. 16-bit 8086 and 8088 b. 32-bit 8086 and 8088 c. 64-bit 8086 and 8088 d. 8-bit 8086 and 8088
Last Answer : a. 16-bit 8086 and 8088
Description : The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these
Last Answer : a. The address of next instruction to be run
Description : In 1-address format how many address is used both as source as well as destination: a. b. 9 a 1 2 3 4
Last Answer : 1
Description : In length instruction some programs wants a complex instruction set containing more instruction, more addressing modes and greater address rang, as in case of a. RISC b. CISC c. Both d. None
Last Answer : b. CISC
Description : An instruction code must specify the address of the__. a. Opecode b. Operand c. Both d. None
Last Answer : b. Operand
Description : A stack pointer is a. a 16-bit register in the microprocessor that indicate the beginning of the stack memory. b. a register that decodes and executes 16-bit arithmetic expression. c. The first memory location where a subroutine address is stored. d. a register in which flag bits are stored
Last Answer : a. a 16-bit register in the microprocessor that indicate the beginning of the stack memory.
Description : For a memory with a 16-bit address space, the addressability is a. 16 bits b. 8 bits c. 2^16 bits d. Cannot be determined
Last Answer : d. Cannot be determined
Description : Calculate the size of memory address space for a 16 bit data and 20 bit address bus. A) 1 MB B) 2 MB C) 3 MB D) 4 MB
Last Answer : Calculate the size of memory address space for a 16 bit data and 20 bit address bus. A) 1 MB B) 2 MB C) 3 MB D) 4 MB
Description : How many address bits are required to represent a 32 K memory (A) 10 bits. (B) 12 bits. (C) 14 bits. (D) 16 bits.
Last Answer : (D) 16 bits.
Description : A memory management system has 64 pages with 512 bytes page size. Physical memory consists of 32 page frames. Number of bits required in logical and physical address are respectively: (1) 14 and 15 (2) 14 and 29 (3) 15 and 14 (4) 16 and 32
Last Answer : (3) 15 and 14
Description : Abinary number with 4 bitsiscalleda_ a. Bit b. Bytes ce. Nibble d. None of these
Last Answer : ce. Nibble
Description : Each device represent : a. 1 bit b. 2 bit c. 3 bit d. 4 bit
Last Answer : a. 1 bit