specify where to get the source and destination operands for the operation specified by the

a. Operand fields and opcode
b. Opcode and operand
c. Source and destination
d. Cpu and memory

1 Answer

Answer :

a. Operand fields and opcode

Related questions

Description : The operation is specified by a binary code known as the a. Operand code b. Opcode c. Source code d. — Allof these

Last Answer : b. Opcode

Description : Two important fields of an instruction are. a. Opcode b. Operand c. Only a d. Botha&b

Last Answer : d. Botha&b

Description : The source/destination of operands can be the_ or one of the general-purpose register: a. Memory b. One c. both d. None of these

Last Answer : a. Memory

Description : Execution of instruction specified by instruction to perform: a. Operation b. Operands c. Both a &b d. None of these

Last Answer : a. Operation

Description : An instruction code must specify the address of the__. a. Opecode b. Operand c. Both d. None

Last Answer : b. Operand

Description : Which are designed to interpret a specified number of instruction code. a. Programmer b. Processors c. Instruction d. Opcode

Last Answer : b. Processors

Description : The instruction set can have variable-length instruction format primarily due to: a. Varying number of operands b. Varying length of opcodes in some CPU ce. Both d. None

Last Answer : ce. Both

Description : Which operation use one operand or unary operations: a. Arithmetic b. Logical c. Both d. None

Last Answer : c. Both

Description : Which operation is used to shift the content of an operand to one or more bits to provide necessary variation: a. Logical and bit manipulation b. Shift manipulation c. Circular manipulation d. None of these

Last Answer : b. Shift manipulation

Description : Given a source code with 10 operators includes 6 unique operators, and 6 operand including 2 unique operands. The program volume is ? 48 120 720 insufficient data

Last Answer : 48

Description : Micro-orders generate the_ __ address of operand and execute instruction and prepare for fetching next instruction from the main memory: a. Physical b. Effective c. Logical d. all of above

Last Answer : b. Effective

Description : In which addressing the simplest addressing mode where an operand is fetched from memory is a. Immediate addressing b. Direct addressing c. Register addressing d. None of these

Last Answer : b. Direct addressing

Description : In which mode the main memory location holds the EA of the operand: a. Immediate addressing b. Direct addressing c. Register addressing d. Indirect addressing

Last Answer : d. Indirect addressing

Description : Ingiven lines of code MOV AX,BL have different type of operands according to assembler for 8086 architecture these identifiers must be of. a. Different type only in byte b. Same type either in word or byte c. Botha &b d. None of these

Last Answer : b. Same type either in word or byte

Description : Opcode is the machine instruction obtained from decoding instruction stored in. a. Stack pointer b. Address pointer Cc. Instruction register d. Incrementer

Last Answer : Cc. Instruction register

Description : What are the four parts of label , opcode , operand and comment ?

Last Answer : Labels , opcodes , operands and comments are the four parts of a mechanical language.

Description : Instruction in computer languages consists of A) OPCODE B) OPERAND C) Both of above D) None of above

Last Answer : Answer : C

Description : Instruction in computer languages consists of a. OPCODE b. OPERAND c. Both of above d. None of above

Last Answer : Both of above

Description : Instruction in computer languages consists of a. OPCODE b. OPERAND c. Both of above d. None of above

Last Answer : c. Both of above

Description : The compiler converts all operands upto the type of the largest operand is called (A) Type Promotion (B) Type Evaluation (C) Type Conversion (D) Type Declaration

Last Answer : (A) Type Promotion 

Description : isacommand given to a computer to perform a specified operation on some given data. a. Aninstruction b. Command c. Code d. None of these

Last Answer : a. Aninstruction

Description : In which addressing the operand is actually present in instruction: a. Immediate addressing b. Direct addressing 9 Register addressing a None of these

Last Answer : a. Immediate addressing

Description : five bits of OPR select one of the operation inthe __ in control register. a. CPU b. RISC ec ALU d. MUX

Last Answer : ec ALU

Description : what is full form of EDSAC: a. Electronic delay source accumulator calculator b. Electronic delay storage automatic code c. Electronic destination source automatic calculator d. Electronic delay storage automatic calculator

Last Answer : d. Electronic delay storage automatic calculator

Description : In 1-address format how many address is used both as source as well as destination: a. b. 9 a 1 2 3 4

Last Answer : 1

Description : Assume a two address format specified as source, destination. Examine the following sequence of instruction and explain the addressing modes used and the operation done in every instruction?

Last Answer : 1. Move (R5) +, R0 2. Add (R5) +, R0. 3. Move (R0), (R5) 4. Move 16(R5), R3 5. Add #40, R5

Description : Which memory is assembled between main memory and CPU: a. Primary memory b. Cache memory Cc. Botha & b d. None of these

Last Answer : b. Cache memory

Description : sis given an instruction in machine language this instruction is fetched from the memory by the CPU to execute: a. ALU b. CPU c. MU d. All of these

Last Answer : b. CPU

Description : In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR

Last Answer : b. CPU

Description : Before checking the program for errors in translating code into machine language the high level language code is loaded into __ a. Register b. Memory c. Data d. CPU

Last Answer : b. Memory

Description : Cache memory is located between main memory and : a. CPU b. Memory c. Botha &b d. None of these

Last Answer : a. CPU

Description : ___uses the stack to store return address of subroutine: a. CPU b. Microprocessor c. register d. memory

Last Answer : b. Microprocessor

Description : The extent nesting in subroutine is limited only by: a. Number of available Stack locations b. Number of available Addressing locations c. Number of available CPU locations d. Number of available Memory locations

Last Answer : a. Number of available Stack locations

Description : The function of these microinstructions is to issue the micro orders to_ _ a. CPU b. Memory c. Register d. Accumulator

Last Answer : a. CPU

Description : Control memory is part of __ that has addressable storage registers and used as temporary storage for data. a. ROM b. RAM c. CPU d. Memory

Last Answer : b. RAM

Description : Which memory is used to copy instructions or data currently used by CPU: a. Main memory b. Secondary memory c. Cache memory d. None of these

Last Answer : c. Cache memory

Description : What are 2 advantages of cache memory: a. Reduction of average access time for CPU memory b. Reduction of bandwidth of available memory of CPU c. Botha&b d. None of these

Last Answer : c. Botha&b

Description : Which functions are performed by CU: a. Data exchange b/w CPU and memory or I/O modules b. External operations c. Internal operations inside CPU d Botha&c

Last Answer : d Botha&c

Description : ___is the data paths link CPU registers with memory or I/O modules. a. External data paths b. Internal data paths c. Boreal data paths d. Exchange data paths

Last Answer : a. External data paths

Description : function select takes op code in IR translating to function of ALU and it may be compact binary code or one line per ALU: a ALU b CPU c. Memory d. Cache

Last Answer : a ALU

Description : A stack in a digital computer isa partofthe_ ALU CPU a. b. c. Memory unit d None of these

Last Answer : c. Memory unit

Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU

Last Answer : b. Main memory

Description : In immediate addressing the operand is placed a. in the CPU register b. after OP code in the instruction c. in memory d. in stack

Last Answer : b. after OP code in the instruction

Description : The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these

Last Answer : a. The address of next instruction to be run

Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read

Last Answer : d. Address register and read

Description : Which are benefit of input/output interrupt: a. It is an external analogy to exceptions b. The processor initiates and perform all I/O operation c. The data is transferred into the memory through interrupt handler d. = Alllof these

Last Answer : d. = Alllof these

Description : Which operations are used for addition, subtraction, increment, decrement and complement function: a. Bus b. Memory transfer c. Arithmetic operation d. Allof these

Last Answer : d. Allof these

Description : In memory read the operation puts memory address on to a register known as : a. PC b. ALU ce. MAR d. — Allof these

Last Answer : ce. MAR

Description : Which operation puts memory address in memory address register and data in DR. a Memory read b. Memory write c Both d. None

Last Answer : b. Memory write

Description : In stack organization address register is known as the: a. Memory stack b. Stack pointer c. Push operation d. Pop operation

Last Answer : b. Stack pointer