Description : IBM-360 type language is example which supporting _—___—sJanguage. a. Micro b. Macro c. Botha &b d. None of these
Last Answer : b. Macro
Description : Process of replacing the sequence of lines of codes is known as: a. Expanding die macro b. Expanding tri macro c. Tetra macro d. None of these
Last Answer : a. Expanding die macro
Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read
Last Answer : d. Address register and read
Description : Which are benefit of input/output interrupt: a. It is an external analogy to exceptions b. The processor initiates and perform all I/O operation c. The data is transferred into the memory through interrupt handler d. = Alllof these
Last Answer : d. = Alllof these
Description : Which operation puts memory address in memory address register and data in DR. a Memory read b. Memory write c Both d. None
Last Answer : b. Memory write
Description : Before checking the program for errors in translating code into machine language the high level language code is loaded into __ a. Register b. Memory c. Data d. CPU
Last Answer : b. Memory
Description : Control memory is part of __ that has addressable storage registers and used as temporary storage for data. a. ROM b. RAM c. CPU d. Memory
Last Answer : b. RAM
Description : Addresses in control memory is made by for each register group: a. Address select logic b. Data select logic c. Control select logic d. All of these
Last Answer : a. Address select logic
Description : What type of circuit is used by control memory to interconnect registers. a. Data routing circuit b. Address routing circuit c. Control routing circuit d. None of the these
Last Answer : a. Data routing circuit
Description : Which memory is used to copy instructions or data currently used by CPU: a. Main memory b. Secondary memory c. Cache memory d. None of these
Last Answer : c. Cache memory
Description : Copy of instruction in cache memory is known as: a Execution cache b. Data cache c. Instruction cache d. Allof these
Last Answer : c. Instruction cache
Description : Copy of data in cache memory is called. a. Datacache b. Execution cache c. Address cache d. Control cache
Last Answer : a. Datacache
Description : In cache memory hit rate indicates. a. Data from requested address is not available b. Data from requested address is available c. Control from requested address is available d. Address from requested address is not available
Last Answer : b. Data from requested address is available
Description : In cache memory miss rate indicates. a. Availability of requested data b. Availability of requested address c. Non-Availability of requested data d. Non-Availability of requested address
Last Answer : c. Non-Availability of requested data
Description : Updating writes to cache data andalsoto___ a. Directories b. Memory c. Registers d. Folders
Last Answer : a. Directories
Description : Various machine level components are: a. Address register > Program counter c Data register d. Accumulator register e. Memory of 2K,16 bits/word RAM f. Multiplexers g. Allof these
Last Answer : g. Allof these
Description : Which functions are performed by CU: a. Data exchange b/w CPU and memory or I/O modules b. External operations c. Internal operations inside CPU d Botha&c
Last Answer : d Botha&c
Description : ___is the data paths link CPU registers with memory or I/O modules. a. External data paths b. Internal data paths c. Boreal data paths d. Exchange data paths
Last Answer : a. External data paths
Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU
Last Answer : b. Main memory
Description : The length of instruction set depends on: a. Data size b. Memory size c. Both d. None
Last Answer : b. Memory size
Description : MIMD stands for: a. Multiple input multiple data b. Memory input multiple data c. Multiple instruction multiple data d. Memory instruction multiple data
Last Answer : c. Multiple instruction multiple data
Description : Which types of register holds a single vector containing at least two read ports and one write ports: a. Data system b. Data base Cc. Memory d. Vector register
Last Answer : d. Vector register
Description : Parallel computing means doing several takes simultaneously thus improving the performance of the a. Data system b. Computer system Cc. Memory d. Vector register
Last Answer : b. Computer system
Description : First think of the person who lives in disguise, Who deals in secrets and tells naught but lies. Next, tell me what's always the last thing to mend, The middle of the middle and end of the ... . Now string them together, and answer me this, Which creature would you be unwilling to kiss? -Riddles
Last Answer : Spider.
Description : First think of a person who lives in disguise, Who deals in secrets and tells naught but lies. Next, tell me what's always the last thing to mend, The middle of middle and end of the end? ... word. Now string them together, and answer me this, Which creature would you be unwilling to kiss? -Riddles
Last Answer : Spider A spy is a person who lives in disguise, Who deals in secrets and tells naught but lies. D is always the last letter in mend, The middle letter of middle and the end letter in end. Er is a ... hard-to-find word. And if you string them together, I doubt you would be willing to kiss a spider!
Description : Next tell me what's always the last thing to mend, the middle of middle and the end of end? -Riddles
Last Answer : D.
Description : emaphore provides mutual exclusion for accesses to the buffer pool and is initialized to the value: a. Mutex b. Mutual Cc. Memory d. __ Allof these
Last Answer : Mutex
Description : Which memory is assembled between main memory and CPU: a. Primary memory b. Cache memory Cc. Botha & b d. None of these
Last Answer : b. Cache memory
Description : specify where to get the source and destination operands for the operation specified by the a. Operand fields and opcode b. Opcode and operand c. Source and destination d. Cpu and memory
Last Answer : a. Operand fields and opcode
Description : The source/destination of operands can be the_ or one of the general-purpose register: a. Memory b. One c. both d. None of these
Last Answer : a. Memory
Description : _is the step during which a new instruction is read from the memory: a Decode b. Fetch c. Execute d. None of these
Last Answer : b. Fetch
Description : The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, ... incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next
Last Answer : c. Instruction register, incremented and next
Description : Which unit acts as the brain of the computer which control other peripherals and interfaces: a. Memory unit b. Cache unit c. Timing and control unit d. None of these
Last Answer : c. Timing and control unit
Description : Which unit works as an interface between the processor and all the memories on chip or off- chip: a. Timing unit b. Control unit c. Memory control unit d All of these
Last Answer : c. Memory control unit
Description : sis given an instruction in machine language this instruction is fetched from the memory by the CPU to execute: a. ALU b. CPU c. MU d. All of these
Last Answer : b. CPU
Description : Which instruction are 32 bits long , with extra 16 bits. a. Memory reference instruction b. Memory reference format c. Both d. None of these
Last Answer : a. Memory reference instruction
Description : Which is addressed by sign extending the 16-bit displacement to 32-bit: a. Memory address b. Effective memory address c. Both a and b d. None of these
Last Answer : b. Effective memory address
Description : Which are instruction in which two machine cycle are required: a. Instruction cycle b. Memory reference instruction c. Both d. None of these
Last Answer : b. Memory reference instruction
Description : Which instruction are used in multithreaded parallel processor architecture. a. Memory reference instruction b. Memory reference format c. Both d. None of these
Description : Which instruction are arranged as per the protocols of memory reference format of the input file in a simple ASCII sequence of integers between the range O to 99 separated by spaces without formatted text ... : a. Memory reference instruction b. Memory reference format c. Both d. None of these
Description : of the primary memory of the computer is limited. a. Storage capacity b. Magnetic disk c. Both d. None of these
Last Answer : a. Storage capacity
Description : Which microprocessor has the control unit, memory unit and arithmetic and logic unit: a. Pentium IV processor b Pentium V processor c. Pentium III processor d. None of these
Last Answer : a. Pentium IV processor
Description : Which operations are used for addition, subtraction, increment, decrement and complement function: a. Bus b. Memory transfer c. Arithmetic operation d. Allof these
Last Answer : d. Allof these
Description : In which transfer the computer register are indicated in capital letters for depicting its function. a. Memory transfer b. Register transfer c. Bus transfer d. None of these
Last Answer : b. Register transfer
Description : The register that includes the address of the memory unit is termed asthe _ a. MAR b PC Cc. IR d. None of these
Last Answer : a. MAR
Description : In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR
Description : In memory read the operation puts memory address on to a register known as : a. PC b. ALU ce. MAR d. — Allof these
Last Answer : ce. MAR
Description : The memory bus is also referred as _ a. Databus b. Address bus c. Memory bus d. — Allof these
Last Answer : a. Databus
Description : How many parts of memory bus: a 2 b 3 c. 5 d. 6
Last Answer : a 2
Description : SDRAM stands for. a. System dynamic random access memory b. Synchronous dynamic random access memory c. Both d. None
Last Answer : b. Synchronous dynamic random access memory