Description : Which memory is assembled between main memory and CPU: a. Primary memory b. Cache memory Cc. Botha & b d. None of these
Last Answer : b. Cache memory
Description : Modern assemblers for RISC based architectures make optimization of instruction scheduling to make use of CPU __ efficiently: a. Pipeline b. Without pipeline c. Botha &b d. None of these
Last Answer : a. Pipeline
Description : Return instruction is written in_ to written to main program: a. Subroutine b. Main program c. Botha &b d. None of these
Last Answer : a. Subroutine
Description : In protocol each process can make a request onlyinan a. Increasing order b. Decreasing order c. Botha &b d. None of these
Last Answer : a. Increasing order
Description : Which state refers to a state that is not safe not necessarily a deadlocked state. a. Safe state b. Unsafe state c. Botha &b d. None of these
Last Answer : b. Unsafe state
Description : Which is one of the important I/O devices and is most commonly used as permanent storage device in any processor: a. Soft disk b. Hard disk c. Botha &b d. None of these
Last Answer : b. Hard disk
Description : which of the 2 files are created by the assembler. a. _ List and object file b. Link and object file c. Botha &b d. None of these
Last Answer : a. _ List and object file
Description : Ingiven lines of code MOV AX,BL have different type of operands according to assembler for 8086 architecture these identifiers must be of. a. Different type only in byte b. Same type either in word or byte c. Botha &b d. None of these
Last Answer : b. Same type either in word or byte
Description : IBM-360 type language is example which supporting _—___—sJanguage. a. Micro b. Macro c. Botha &b d. None of these
Last Answer : b. Macro
Description : address is not assigned by linker. a. Absolute b. Relative c. Botha &b a None of these
Last Answer : a. Absolute
Description : shave addresses where instructions are stored along with address of working storage: a. _ Relative entities b. Absolute entities c. Botha &b d. None of these
Last Answer : a. _ Relative entities
Description : Full form of MIPS assembler is: a. Microprocessor without interlocked pipeline stage b. Microprocessor with interlocked pipeline stage c. Botha &b d. None of these
Last Answer : a. Microprocessor without interlocked pipeline stage
Description : Ina complex program, the overlaps: a. Branching b. Condition c. Botha &b d. None of these
Last Answer : a. Branching
Description : Avoid crossing flow lines. a. Flowchart b. Algorithm c. Botha &b d. None of these
Last Answer : a. Flowchart
Description : is useful to prepare detailed program documentation: a. Flowchart b. Algorithm c. Botha &b d. None of these
Description : subroutine declaration come after procedure announcement: a. Global b. Local c. Botha &b d. None of these
Last Answer : a. Global
Description : Callis_ subroutine call. a. Conditional b. Unconditi c. Botha &b d. None of these
Last Answer : b. Unconditi
Description : The processed data is sent for output to standard __ device which by default is computer screen: a. Input b. Output c. Botha &b d. None of these
Last Answer : b. Output
Description : Each instruction is executed by set of micro operations termed as. a. Micro instructions b. Mini instructions c. Botha &b d. None of these
Last Answer : a. Micro instructions
Description : which of the following is interrupt mode. a. Task mode b. Executive mode c. Botha &b d. None of these
Last Answer : b. Executive mode
Description : Which memory is used to copy instructions or data currently used by CPU: a. Main memory b. Secondary memory c. Cache memory d. None of these
Last Answer : c. Cache memory
Description : What are 2 advantages of cache memory: a. Reduction of average access time for CPU memory b. Reduction of bandwidth of available memory of CPU c. Botha&b d. None of these
Last Answer : c. Botha&b
Description : function select takes op code in IR translating to function of ALU and it may be compact binary code or one line per ALU: a ALU b CPU c. Memory d. Cache
Last Answer : a ALU
Description : A computer having writable control memory is known as_ a. Static micro programmable b. Dynamic micro programmable c. Botha & b d. None of these
Last Answer : b. Dynamic micro programmable
Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU
Last Answer : b. Main memory
Description : Which unit acts as the brain of the computer which control other peripherals and interfaces: a. Memory unit b. Cache unit c. Timing and control unit d. None of these
Last Answer : c. Timing and control unit
Description : Copy of instruction in cache memory is known as: a Execution cache b. Data cache c. Instruction cache d. Allof these
Last Answer : c. Instruction cache
Description : Copy of data in cache memory is called. a. Datacache b. Execution cache c. Address cache d. Control cache
Last Answer : a. Datacache
Description : On what method search in cache memory used by the system. a. Cache directing b. Cache mapping c. Cache controlling d. Cache invalidation
Last Answer : b. Cache mapping
Description : In cache memory hit rate indicates. a. Data from requested address is not available b. Data from requested address is available c. Control from requested address is available d. Address from requested address is not available
Last Answer : b. Data from requested address is available
Description : In cache memory miss rate indicates. a. Availability of requested data b. Availability of requested address c. Non-Availability of requested data d. Non-Availability of requested address
Last Answer : c. Non-Availability of requested data
Description : Updating writes to cache data andalsoto___ a. Directories b. Memory c. Registers d. Folders
Last Answer : a. Directories
Description : The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these
Last Answer : a. The address of next instruction to be run
Description : Execution of instruction specified by instruction to perform: a. Operation b. Operands c. Both a &b d. None of these
Last Answer : a. Operation
Description : function is used to transfer the control to end of a program which uses one argument( ) and takes value is zero for_ __ termination and non-zero for _termination: a. _ Exit( ) normal, abnormal b. Break, normal, abnormal Botha & b None of these
Last Answer : a. _ Exit( ) normal, abnormal
Description : getchar :: IO char in this given function what is indicated by IO char: a. when getchar is invoked it returns a character b. when getchar is executed it returns a character c. botha & b d. none of these
Last Answer : a. when getchar is invoked it returns a character
Description : state keeps track of position related to execution of an instruction: a. Major b. Minor c. Botha & b d. None of these
Last Answer : a. Major
Description : specify where to get the source and destination operands for the operation specified by the a. Operand fields and opcode b. Opcode and operand c. Source and destination d. Cpu and memory
Last Answer : a. Operand fields and opcode
Description : sis given an instruction in machine language this instruction is fetched from the memory by the CPU to execute: a. ALU b. CPU c. MU d. All of these
Last Answer : b. CPU
Description : In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR
Description : Before checking the program for errors in translating code into machine language the high level language code is loaded into __ a. Register b. Memory c. Data d. CPU
Last Answer : b. Memory
Description : ___uses the stack to store return address of subroutine: a. CPU b. Microprocessor c. register d. memory
Last Answer : b. Microprocessor
Description : The extent nesting in subroutine is limited only by: a. Number of available Stack locations b. Number of available Addressing locations c. Number of available CPU locations d. Number of available Memory locations
Last Answer : a. Number of available Stack locations
Description : The function of these microinstructions is to issue the micro orders to_ _ a. CPU b. Memory c. Register d. Accumulator
Last Answer : a. CPU
Description : Control memory is part of __ that has addressable storage registers and used as temporary storage for data. a. ROM b. RAM c. CPU d. Memory
Last Answer : b. RAM
Description : Which functions are performed by CU: a. Data exchange b/w CPU and memory or I/O modules b. External operations c. Internal operations inside CPU d Botha&c
Last Answer : d Botha&c
Description : ___is the data paths link CPU registers with memory or I/O modules. a. External data paths b. Internal data paths c. Boreal data paths d. Exchange data paths
Last Answer : a. External data paths
Description : A stack in a digital computer isa partofthe_ ALU CPU a. b. c. Memory unit d None of these
Last Answer : c. Memory unit
Description : Which of the following correctly lists computer memory types from highest to lowest speed? (A) Secondary Storage: Main Memory (RAM); Cache. Memory; CPU Registers (B) CPU Registers; Cache Memory; ... (RAM); Secondary Storage (D) Cache Memory; CPU Registers; Main Memory (RAM); Secondary Storage
Last Answer : Answer: C (CPU Registers > Cache Memory > Main Memory (RAM) > Secondary Storage)
Description : When cache process starts hit and miss rate defines in cache directory: a. during search reads b. during search writes c. during replace writes d. during finding writes
Last Answer : a. during search reads