Description : Copy of instruction in cache memory is known as: a Execution cache b. Data cache c. Instruction cache d. Allof these
Last Answer : c. Instruction cache
Description : In cache memory hit rate indicates. a. Data from requested address is not available b. Data from requested address is available c. Control from requested address is available d. Address from requested address is not available
Last Answer : b. Data from requested address is available
Description : Which memory is used to copy instructions or data currently used by CPU: a. Main memory b. Secondary memory c. Cache memory d. None of these
Last Answer : c. Cache memory
Description : In cache memory miss rate indicates. a. Availability of requested data b. Availability of requested address c. Non-Availability of requested data d. Non-Availability of requested address
Last Answer : c. Non-Availability of requested data
Description : Which unit acts as the brain of the computer which control other peripherals and interfaces: a. Memory unit b. Cache unit c. Timing and control unit d. None of these
Last Answer : c. Timing and control unit
Description : Updating writes to cache data andalsoto___ a. Directories b. Memory c. Registers d. Folders
Last Answer : a. Directories
Description : Which microinstruction provide next instruction from control memory: a. Microinstruction execution b. Microinstruction Buffer c. Microinstruction decoder d. Microinstraction Sequencing
Last Answer : d. Microinstraction Sequencing
Description : During program execution content of main memory undergo changes and, but control memory has _ microprogram: a. Static b. Dynamic c. Compile time d. Fixed
Last Answer : d. Fixed
Description : Addresses in control memory is made by for each register group: a. Address select logic b. Data select logic c. Control select logic d. All of these
Last Answer : a. Address select logic
Description : What type of circuit is used by control memory to interconnect registers. a. Data routing circuit b. Address routing circuit c. Control routing circuit d. None of the these
Last Answer : a. Data routing circuit
Description : When subroutine is called contents of program counter is location address of __ instruction following call instruction is stored on _ __and program execution is transferred to __ address. a. Non ... , Stack and Main program Cc. Executable, Queue and Subroutine d. Executable, Stack and Subroutine
Last Answer : d. Executable, Stack and Subroutine
Description : Which memory is assembled between main memory and CPU: a. Primary memory b. Cache memory Cc. Botha & b d. None of these
Last Answer : b. Cache memory
Description : Cache memory is located between main memory and : a. CPU b. Memory c. Botha &b d. None of these
Last Answer : a. CPU
Description : What are 2 advantages of cache memory: a. Reduction of average access time for CPU memory b. Reduction of bandwidth of available memory of CPU c. Botha&b d. None of these
Last Answer : c. Botha&b
Description : On what method search in cache memory used by the system. a. Cache directing b. Cache mapping c. Cache controlling d. Cache invalidation
Last Answer : b. Cache mapping
Description : function select takes op code in IR translating to function of ALU and it may be compact binary code or one line per ALU: a ALU b CPU c. Memory d. Cache
Last Answer : a ALU
Description : The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these
Last Answer : a. The address of next instruction to be run
Description : How many modes the address in control memory are divided. a 2 b 3 c. 5 d 7
Last Answer : a 2
Description : The time required to complete one instruction is called. a. Fetch time b. Execution time c. Control time d. All of these
Last Answer : b. Execution time
Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read
Last Answer : d. Address register and read
Description : Which operation puts memory address in memory address register and data in DR. a Memory read b. Memory write c Both d. None
Last Answer : b. Memory write
Description : Various machine level components are: a. Address register > Program counter c Data register d. Accumulator register e. Memory of 2K,16 bits/word RAM f. Multiplexers g. Allof these
Last Answer : g. Allof these
Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU
Last Answer : b. Main memory
Description : Which is the method by which instructions are selected for execution: a. Instruction selection b. — Selection control c. Instraction sequencing d. All of these
Last Answer : c. Instraction sequencing
Description : Which unit is necessary for the execution of instruction: a. Timing b. Control ce. Both d. None of these
Last Answer : ce. Both
Description : Ininstruction formats the information required by the _ for execution: a. ALU b. CPU Cc. RISC d. DATA
Last Answer : b. CPU
Description : is a symbolic representation of discrete elements of information: a. Data b. Code c. Address d. Control
Last Answer : b. Code
Description : For each micro operation the control unit generates set of_ signals. a. Control b. Address c. Data d. None of these
Last Answer : a. Control
Description : Which control refers to the track of the address of instructions. a. Data control b. Register control c. Program control d. None of these
Last Answer : c. Program control
Description : When cache process starts hit and miss rate defines in cache directory: a. during search reads b. during search writes c. during replace writes d. during finding writes
Last Answer : a. during search reads
Description : Which 3 areas are used by cache process: a. Search, updating, invalidation b. Write, updating, invalidation c. Search, read, updating d. —_Invalidation, updating, requesting
Last Answer : a. Search, updating, invalidation
Description : Which one of the following statements is false regarding the Distributed Cache? a) The Hadoop framework will ensure that any files in the Distributed Cache are distributed to all map and reduce tasks. b) ... Cache on to the slave node before any tasks for the job are executed on that node.
Last Answer : MapReduce tries to place the data and the compute as close as possible
Description : Control memory is part of __ that has addressable storage registers and used as temporary storage for data. a. ROM b. RAM c. CPU d. Memory
Last Answer : b. RAM
Description : The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, ... incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next
Last Answer : c. Instruction register, incremented and next
Description : Which is addressed by sign extending the 16-bit displacement to 32-bit: a. Memory address b. Effective memory address c. Both a and b d. None of these
Last Answer : b. Effective memory address
Description : The register that includes the address of the memory unit is termed asthe _ a. MAR b PC Cc. IR d. None of these
Last Answer : a. MAR
Description : In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR
Description : In memory read the operation puts memory address on to a register known as : a. PC b. ALU ce. MAR d. — Allof these
Last Answer : ce. MAR
Description : The memory bus is also referred as _ a. Databus b. Address bus c. Memory bus d. — Allof these
Last Answer : a. Databus
Description : ___uses the stack to store return address of subroutine: a. CPU b. Microprocessor c. register d. memory
Last Answer : b. Microprocessor
Description : Micro-orders generate the_ __ address of operand and execute instruction and prepare for fetching next instruction from the main memory: a. Physical b. Effective c. Logical d. all of above
Last Answer : b. Effective
Description : Invalidation writes only to___ and erases previously residing address in memory: a. Folders b. Memory c. Directory d. Files
Last Answer : c. Directory
Description : In stack organization address register is known as the: a. Memory stack b. Stack pointer c. Push operation d. Pop operation
Last Answer : b. Stack pointer
Description : Memory —mapped ___is used this is just another memory address. a. Input b. Output c. Both d. None
Last Answer : c. Both
Description : In post-indexing the contents of the address field are used to access a memory location containing a___ address: Immediate addressing Direct addressing Register addressing ao | None of these
Last Answer : Direct addressing
Description : Execution of instruction specified by instruction to perform: a. Operation b. Operands c. Both a &b d. None of these
Last Answer : a. Operation
Description : Which is the main function of the computer. a. Execute of programs b. Execution of programs c. Both d. None of these
Last Answer : b. Execution of programs
Description : Assembler works to convert assembly language program into machine language : a. Before the computer can execute it b. After the computer can execute it c. In between execution d. All of these
Last Answer : a. Before the computer can execute it
Description : Which of the following 2 task are performed to execute an instruction by MCU: a. Microinstruction execution b. Microinstruction sequencing c. Botha&b d. None of these
Description : state keeps track of position related to execution of an instruction: a. Major b. Minor c. Botha & b d. None of these
Last Answer : a. Major