The Command to access the memory or the I/O device is carried by ______ A. Address Bus B. Data Bus C. Control Bus D. None of the Above

The Command to access the memory or the I/O device is carried by ______ A. Address Bus B. Data Bus C. Control Bus D. None of the Above
by

1 Answer

Answer :

C. Control Bus
by
selected

Related questions

The communication between the components in a microcomputer takes place via the address and ______ A. I/O bus B. Data bus C. Address bus D. None of the Above

Description : The communication between the components in a microcomputer takes place via the address and ______ A. I/O bus B. Data bus C. Address bus D. None of the Above

Last Answer : B. Data bus

Storage device where time to retrieve stored information is independent of address where it is stored is called _______ A. Random Access Memory B. Secondary Memory C. System D. None of the above

Description : Storage device where time to retrieve stored information is independent of address where it is stored is called _______ A. Random Access Memory B. Secondary Memory C. System D. None of the above

Last Answer : A. Random Access Memory

Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU: a. Control bus b. Data bus c. Address bus d. None of these

Description : Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU: a. Control bus b. Data bus c. Address bus d. None of these

Last Answer : a. Control bus

The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus

Description : The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus

Last Answer : a. Address bus

A 32-bit address bus allows access to a memory of capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb 2.Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors

Description : A 32-bit address bus allows access to a memory of capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb 2.Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors

Last Answer : c) all x86 processors

A 20-bit address bus allows access to a memory of capacity

Description : A 20-bit address bus allows access to a memory of capacity  (1) 1 Mb (2) 2 Mb (3) 32 Mb (4) 64 Mb 

Last Answer : 1MB

The necessary steps carried out to perform the operation of accessing either memory or I/O Device, constitute a ___________________ a) fetch operation b) execute operation c) machine cycle

Description : The necessary steps carried out to perform the operation of accessing either memory or I/O Device, constitute a ___________________ a) fetch operation b) execute operation c) machine cycle

Last Answer : c) machine cycle

The contents of information are stored in A) Memory data register B) Memory address register C) Memory arithmetic registers D) Memory access register

Description : The contents of information are stored in A) Memory data register B) Memory address register C) Memory arithmetic registers D) Memory access register

Last Answer : Answer : A

The contents of information are stored in _______: a) Memory Data Register b) Memory Address Register c) Memory Access Register d) Memory Arithmetic Register e) None of The Above

Description : The contents of information are stored in _______: a) Memory Data Register b) Memory Address Register c) Memory Access Register d) Memory Arithmetic Register e) None of The Above

Last Answer : a) Memory Data Register

The contents of information are stored in --- 1) Memory data register 2) Memory address register 3) Memory access register 4) Memory arithmetic register

Description : The contents of information are stored in --- 1) Memory data register 2) Memory address register 3) Memory access register 4) Memory arithmetic register

Last Answer : 1) Memory data register

A bus that transfer data from one component to another or between computers is called _________ A. Address Bus B. Data Bus C. Control Bus D. None of the Above

Description : A bus that transfer data from one component to another or between computers is called _________ A. Address Bus B. Data Bus C. Control Bus D. None of the Above

Last Answer : B. Data Bus

A computer bus that is used to specify a Physical address? A. Address Bus B. Data Bus C. Control Bus D. None of the Above

Description : A computer bus that is used to specify a Physical address? A. Address Bus B. Data Bus C. Control Bus D. None of the Above

Last Answer : A. Address Bus

An interface that provides I/O transfer of data directly to and form the memory unit and peripheral is termed as________ A. DDA B. Serial interface C. Direct Memory Access (DMA) D. None of the Above

Description : An interface that provides I/O transfer of data directly to and form the memory unit and peripheral is termed as________ A. DDA B. Serial interface C. Direct Memory Access (DMA) D. None of the Above

Last Answer : C. Direct Memory Access (DMA)

The hardware in which data may be stored for a computer system is called ________ A. Registers B. Bus C. Control Unit D. Memory

Description : The hardware in which data may be stored for a computer system is called ________ A. Registers B. Bus C. Control Unit D. Memory

Last Answer : D. Memory

A physical connection between the microprocessor memory and other parts of the microcomputer is known as A) Path B) Address bus C) Route D) All of the above

Description : A physical connection between the microprocessor memory and other parts of the microcomputer is known as A) Path B) Address bus C) Route D) All of the above

Last Answer : Answer : B

Which bus plays a crucial role in I/O: a. System bus b. Control bus c. Address bus d. Both A and B

Description : Which bus plays a crucial role in I/O: a. System bus b. Control bus c. Address bus d. Both A and B

Last Answer : b. Control bus

ACL stands for. a. Application Control Language b. Application Control list c. Access control List d. Access Command List

Description : ACL stands for. a. Application Control Language b. Application Control list c. Access control List d. Access Command List

Last Answer : d. Access Command List

Calculate the size of memory address space for a 16 bit data and 20 bit address bus.

Description : Calculate the size of memory address space for a 16 bit data and 20 bit address bus. A) 1 MB B) 2 MB C) 3 MB D) 4 MB

Last Answer : Calculate the size of memory address space for a 16 bit data and 20 bit address bus. A) 1 MB B) 2 MB C) 3 MB D) 4 MB

Through which device the main components of the computer communicate with each other? A) Keyboard B) System Bus C) Monitor D) Memory

Description : Through which device the main components of the computer communicate with each other? A) Keyboard B) System Bus C) Monitor D) Memory

Last Answer : Answer : B

The register which holds the address of the location to or from which data are to be transferred is known as_______ A. Instruction Register B. Control register C. Memory Address Register D. None of the Above

Description : The register which holds the address of the location to or from which data are to be transferred is known as_______ A. Instruction Register B. Control register C. Memory Address Register D. None of the Above

Last Answer : C. Memory Address Register

What does MAR stand for? a) Main Address Register b) Memory Access Register c) Main Accessible Register d) Memory Address Register

Description : What does MAR stand for? a) Main Address Register b) Memory Access Register c) Main Accessible Register d) Memory Address Register

Last Answer : Answer: d Explanation: MAR is a type of register which is responsible for the fetch operation. MAR is connected to the address bus and it specifies the address for the read and write operations

Memories in which any location can be reached in a fixed amount of time after specifying its address is called ________ A. Sequential Access Memory B. Random Access Memory C. Quick Access Memory D. Mass storage

Description : Memories in which any location can be reached in a fixed amount of time after specifying its address is called ________ A. Sequential Access Memory B. Random Access Memory C. Quick Access Memory D. Mass storage

Last Answer : B. Random Access Memory

Technique of using disk space to make programs believe that the system contains more Random Access Memory(RAM) than is actually available is called ______ A. Random Access Memory B. Primary Memory C. Secondary Memory D. Virtual Memory

Description : Technique of using disk space to make programs believe that the system contains more Random Access Memory(RAM) than is actually available is called ______ A. Random Access Memory B. Primary Memory C. Secondary Memory D. Virtual Memory

Last Answer : D. Virtual Memory

What is MAC ? A computer made by Apple Memory address corruption Mediocre Apple Computer Media Access Control

Description : What is MAC ? A computer made by Apple Memory address corruption Mediocre Apple Computer Media Access Control

Last Answer : Media Access Control

The decoded instruction is stored in ______ (A) Register (B) Memory Address Register(MAR) (C) Instruction Register(IR) (D) None of the Above

Description : The decoded instruction is stored in ______ (A) Register (B) Memory Address Register(MAR) (C) Instruction Register(IR) (D) None of the Above

Last Answer : (C) Instruction Register(IR)

Both the ALU and Control Section have special purpose storage locations called : (1) Registers (2) Accumulators (3) Bus (4) Address

Description : Both the ALU and Control Section have special purpose storage locations called : (1) Registers (2) Accumulators (3) Bus (4) Address

Last Answer : Registers

Offline device is A) A device which is not connected to CPU B) A device which is connected to CPU C) A direct access storage device D) An I/O device

Description : Offline device is A) A device which is not connected to CPU B) A device which is connected to CPU C) A direct access storage device D) An I/O device

Last Answer : Answer : A

Which of the following buses available on computer system: a) Address Bus b) Data Bus c) System Bus d) All of Above e) None of These

Description : Which of the following buses available on computer system: a) Address Bus b) Data Bus c) System Bus d) All of Above e) None of These

Last Answer : d) All of Above

System Bus Contains: a. Address Bus b. Data Bus c. Control Bus d. All of these

Description : System Bus Contains: a. Address Bus b. Data Bus c. Control Bus d. All of these

Last Answer : d. All of these

The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.A.control busB.control instructionsC. address decoder D.CPU

Description : The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.A.control busB.control instructionsC. address decoder D.CPU

Last Answer : C. address decoder

CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these

Description : CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these

Last Answer : b. Data bus

Which bus carry addresses: a. System bus b. Address bus c. Control bus d. Data bus

Description : Which bus carry addresses: a. System bus b. Address bus c. Control bus d. Data bus

Last Answer : b. Address bus

______ is the first layer of software loaded into computer memory when it starts up. A. Device Drivers B. Language translators C. System Utilities D. Operating system

Description : ______ is the first layer of software loaded into computer memory when it starts up. A. Device Drivers B. Language translators C. System Utilities D. Operating system

Last Answer : D. Operating system

A high speed device used in CPU for temporary storage during processing is called: a) A register b) A Data Bus c) All of The Above d) None of The Above

Description : A high speed device used in CPU for temporary storage during processing is called: a) A register b) A Data Bus c) All of The Above d) None of The Above

Last Answer : a) A register

The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Fully decoding b. Half decoding c. Both a & b d. None of these

Description : The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Fully decoding b. Half decoding c. Both a & b d. None of these

Last Answer : a. Fully decoding

Which of the following are the two main components of the CPU? A) Control Unit and Registers B) Registers and Main Memory C) Control unit and ALU D) ALU and bus

Description : Which of the following are the two main components of the CPU? A) Control Unit and Registers B) Registers and Main Memory C) Control unit and ALU D) ALU and bus

Last Answer : Answer : C

Which of the following is an example of an optical disk? 1) Magnetic disks 2) Memory disks 3) Data bus disks 4) Digital versatile disks

Description : Which of the following is an example of an optical disk? 1) Magnetic disks 2) Memory disks 3) Data bus disks 4) Digital versatile disks

Last Answer : 4) Digital versatile disks

Which of the following is an example of an optical disk? 1 Magnetic disks 2 Memory disks 3 Data bus disks 4 Digital versatile disks

Description : Which of the following is an example of an optical disk? 1 Magnetic disks 2 Memory disks 3 Data bus disks 4 Digital versatile disks

Last Answer : 4 Digital versatile disks

Which are the causes of the interrupt: a. In any single device b. In processor poll devices c. In a device whose ID number is stored on the address bus d. Allof these

Description : Which are the causes of the interrupt: a. In any single device b. In processor poll devices c. In a device whose ID number is stored on the address bus d. Allof these

Last Answer : d. Allof these

In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR

Description : In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR

Last Answer : b. CPU

The memory bus is also referred as _ a. Databus b. Address bus c. Memory bus d. — Allof these

Description : The memory bus is also referred as _ a. Databus b. Address bus c. Memory bus d. — Allof these

Last Answer : a. Databus

A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above

Description : A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above

Last Answer : b. Address bus

Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these

Description : Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these

Last Answer : a. MAR

A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above

Description : A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above

Last Answer : b. Address bus

A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above

Description : A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above

Last Answer : b. Address bus

The microprocessor can read/write 16 bit data from or to ________ A. memory B. I /O device C. processor D. register

Description : The microprocessor can read/write 16 bit data from or to ________ A. memory B. I /O device C. processor D. register

Last Answer : The microprocessor can read/write 16 bit data from or to memory 

The portion of physical layer that interfaces with the media access control sublayer is called ___________ a. physical signalling sublayer b. physical data sublayer c. physical address sublayer d. physical transport sublayer

Description : The portion of physical layer that interfaces with the media access control sublayer is called ___________ a. physical signalling sublayer b. physical data sublayer c. physical address sublayer d. physical transport sublayer

Last Answer : a. physical signalling sublayer

A storage device or medium where the access time is dependent upon the location of the data is called ________ A. Parallel access B. Serial access C. Both (A) and (B) D. None of the above

Description : A storage device or medium where the access time is dependent upon the location of the data is called ________ A. Parallel access B. Serial access C. Both (A) and (B) D. None of the above

Last Answer : B. Serial access

________ is the ability of a device to ‘jump’ directly to the requested data A. Sequential access B. Random access C. Quick access D. None of the Above

Description : ________ is the ability of a device to ‘jump’ directly to the requested data A. Sequential access B. Random access C. Quick access D. None of the Above

Last Answer : B. Random access