Which bus plays a crucial role in I/O: a. System bus b. Control bus c. Address bus d. Both A and B

Which bus plays a crucial role in I/O:
a. System bus
b. Control bus
c. Address bus
d. Both A and B
by

1 Answer

Answer :

b. Control bus
by

Related questions

System Bus Contains: a. Address Bus b. Data Bus c. Control Bus d. All of these

Description : System Bus Contains: a. Address Bus b. Data Bus c. Control Bus d. All of these

Last Answer : d. All of these

The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus

Description : The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus

Last Answer : a. Address bus

Which bus carry addresses: a. System bus b. Address bus c. Control bus d. Data bus

Description : Which bus carry addresses: a. System bus b. Address bus c. Control bus d. Data bus

Last Answer : b. Address bus

Which application-level protocol plays a crucial role in carrying out the data definition and manipulation in addition to X-500 features? a. TCP b. LDAP c. FTP d. None of the above

Description : Which application-level protocol plays a crucial role in carrying out the data definition and manipulation in addition to X-500 features? a. TCP b. LDAP c. FTP d. None of the above

Last Answer : b. LDAP

The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.A.control busB.control instructionsC. address decoder D.CPU

Description : The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.A.control busB.control instructionsC. address decoder D.CPU

Last Answer : C. address decoder

Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU: a. Control bus b. Data bus c. Address bus d. None of these

Description : Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU: a. Control bus b. Data bus c. Address bus d. None of these

Last Answer : a. Control bus

CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these

Description : CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these

Last Answer : b. Data bus

In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode

Description : In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode

Last Answer : c) bus width select

In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode

Description : In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode

Last Answer : b) address valid strobe select

The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Fully decoding b. Half decoding c. Both a & b d. None of these

Description : The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Fully decoding b. Half decoding c. Both a & b d. None of these

Last Answer : a. Fully decoding

A 32-bit address bus allows access to a memory of capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb 2.Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors

Description : A 32-bit address bus allows access to a memory of capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb 2.Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors

Last Answer : c) all x86 processors

A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above

Description : A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above

Last Answer : b. Address bus

Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these

Description : Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these

Last Answer : a. MAR

In linear decoding address bus of 16-bit wide can connect only ____ of RAM. a. 16 KB b. 6KB c. 12KB d. 64KB

Description : In linear decoding address bus of 16-bit wide can connect only ____ of RAM. a. 16 KB b. 6KB c. 12KB d. 64KB

Last Answer : b. 6KB

The capacity of this chip is 1KB they are organized in the form of 1024 words with 8 bit word The what is the site of address bus: a. 8 bit b. 10 bit c. 12 bit d. 16 bit

Description : The capacity of this chip is 1KB they are organized in the form of 1024 words with 8 bit word The what is the site of address bus: a. 8 bit b. 10 bit c. 12 bit d. 16 bit

Last Answer : b. 10 bit

The processor 80386/80486 and the Pentium processor uses _____ bits address bus: a. 16 b. 32 c. 36 d. 64

Description : The processor 80386/80486 and the Pentium processor uses _____ bits address bus: a. 16 b. 32 c. 36 d. 64

Last Answer : b. 32

A 16 bit address bus can generate___ addresses: a. 32767 b. 25652 c. 65536 d. none of these

Description : A 16 bit address bus can generate___ addresses: a. 32767 b. 25652 c. 65536 d. none of these

Last Answer : c. 65536

If ______input pin of 80386 if activated, allows address pipelining during 80386 bus cycles. a) BS16 b) NA c) PEREQ d) ADS

Description : If ______input pin of 80386 if activated, allows address pipelining during 80386 bus cycles. a) BS16 b) NA c) PEREQ d) ADS

Last Answer : a) BS16

What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width

Description : What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width

Last Answer : c) Address bus width

In 8086 microprocessor , the address bus is ________ bit wide A. 12 bit B. 10 bit C. 16 bit D. 20 bit

Description : In 8086 microprocessor , the address bus is ________ bit wide A. 12 bit B. 10 bit C. 16 bit D. 20 bit

Last Answer : In 8086 microprocessor, the address bus is 20 bit

The advantage of memory mapped I/O over I/O mapped I/O is, a) Faster b) Many instructions supporting memory mapped I/O c) Require a bigger address decoder d) All the above

Description : The advantage of memory mapped I/O over I/O mapped I/O is, a) Faster b) Many instructions supporting memory mapped I/O c) Require a bigger address decoder d) All the above

Last Answer : d) All the above

What type of control pins are needed in a microprocessor to regulate traffic on the bus, in order to prevent two devices from trying to use it at the same time? a. Bus control b. Interrupts c. Bus arbitration d. Status

Description : What type of control pins are needed in a microprocessor to regulate traffic on the bus, in order to prevent two devices from trying to use it at the same time? a. Bus control b. Interrupts c. Bus arbitration d. Status

Last Answer : c. Bus arbitration

Which of the following is used for manufacturing chips? a. Control bus b. Control unit c. Parity unit d. Semiconductor

Description : Which of the following is used for manufacturing chips? a. Control bus b. Control unit c. Parity unit d. Semiconductor

Last Answer : d. Semiconductor

Which is used for manufacturing chips? a. Bus b. Control unit c. Semiconductors d. A and b only

Description : Which is used for manufacturing chips? a. Bus b. Control unit c. Semiconductors d. A and b only

Last Answer : c. Semiconductors

Which of the following are the two main components of the CPU? a. Control unit and registers b. Registers and main memory c. Control Unit and ALU d. ALU and bus

Description : Which of the following are the two main components of the CPU? a. Control unit and registers b. Registers and main memory c. Control Unit and ALU d. ALU and bus

Last Answer : c. Control Unit and ALU

The CPU completes yields control of the bus to the DMA controller via: a. DMA acknowledge signal b. DMA integrated signal c. DMA implicitly signal d. None of these

Description : The CPU completes yields control of the bus to the DMA controller via: a. DMA acknowledge signal b. DMA integrated signal c. DMA implicitly signal d. None of these

Last Answer : a. DMA acknowledge signal

Which is not the control bus signal: a. READ b. WRITE c. RESET

Description : Which is not the control bus signal: a. READ b. WRITE c. RESET

Last Answer : c. RESET

Which are the READ operation can in simple steps: a. Address b. Data c. Control d. All of these

Description : Which are the READ operation can in simple steps: a. Address b. Data c. Control d. All of these

Last Answer : d. All of these

The point where control returns after a subprogram is completed is known as the : a. Return address b. Main Address c. Program Address d. Current Address

Description : The point where control returns after a subprogram is completed is known as the : a. Return address b. Main Address c. Program Address d. Current Address

Last Answer : a. Return address

The ____ place the data from a register onto the data bus: a. CPU b. ALU c. Both A and B d. None of these

Description : The ____ place the data from a register onto the data bus: a. CPU b. ALU c. Both A and B d. None of these

Last Answer : a. CPU

The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B

Description : The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B

Last Answer : b. Write

The network of wires or electronic path ways on mother board back side: a. PCB b. BUS c. BOTH A and B d. None of these

Description : The network of wires or electronic path ways on mother board back side: a. PCB b. BUS c. BOTH A and B d. None of these

Last Answer : c. BOTH A and B

The Command to access the memory or the I/O device is carried by ______ A. Address Bus B. Data Bus C. Control Bus D. None of the Above

Description : The Command to access the memory or the I/O device is carried by ______ A. Address Bus B. Data Bus C. Control Bus D. None of the Above

Last Answer : C. Control Bus

Which is the components of computer: a. System Bus b. CPU c. Memory Unit d. All of these

Description : Which is the components of computer: a. System Bus b. CPU c. Memory Unit d. All of these

Last Answer : d. All of these

The external system bus architecture is created using from ______ architecture: a. Pascal b. Dennis Ritchie c. Charles Babbage d. Von Neumann

Description : The external system bus architecture is created using from ______ architecture: a. Pascal b. Dennis Ritchie c. Charles Babbage d. Von Neumann

Last Answer : d. Von Neumann

standard I/O uses which control pin on the micro processor: a. IO/M

Description : standard I/O uses which control pin on the micro processor: a. IO/M

Last Answer : a. IO/M

In 8255, under the I/O mode of operation we have __ modes. Under which mode will have the following features i) A 5 bit control port is available. ii) Three I/O lines are available at Port C. a) 3, Mode2 b) 2, Mode 2 c) 4, Mode 3 d) 3, Mode 2

Description : In 8255, under the I/O mode of operation we have __ modes. Under which mode will have the following features i) A 5 bit control port is available. ii) Three I/O lines are available at Port C. a) 3, Mode2 b) 2, Mode 2 c) 4, Mode 3 d) 3, Mode 2

Last Answer : a) 3, Mode2

Dot-matrix is a type of a. Tape e. Printer f. Disk g. Bus

Description : Dot-matrix is a type of a. Tape e. Printer f. Disk g. Bus

Last Answer : e. Printer

The information on the data bus is transferred to the ______register: a. MOC b. MDR c. VAM d. CPU

Description : The information on the data bus is transferred to the ______register: a. MOC b. MDR c. VAM d. CPU

Last Answer : b. MDR

Which Bus connects CPU & level 2 cache: a. Rear side bus b. Front side bus c. Memory side bus d. None of these

Description : Which Bus connects CPU & level 2 cache: a. Rear side bus b. Front side bus c. Memory side bus d. None of these

Last Answer : b. Front side bus

Which is called superhighway: a. Processor b. Multiplexer c. Backbone bus d. None of these

Description : Which is called superhighway: a. Processor b. Multiplexer c. Backbone bus d. None of these

Last Answer : c. Backbone bus

_____ a subsystem that transfer data between computer components inside a computer or between computer: a. Chip b. Register c. Processor d. Bus

Description : _____ a subsystem that transfer data between computer components inside a computer or between computer: a. Chip b. Register c. Processor d. Bus

Last Answer : d. Bus

To prevent another master from taking over the bus during a critical operation, the 486 can assert its _____signal. a) LOCK# or PLOCK# b) HOLD or BOFF c) HLDA d) HOLD

Description : To prevent another master from taking over the bus during a critical operation, the 486 can assert its _____signal. a) LOCK# or PLOCK# b) HOLD or BOFF c) HLDA d) HOLD

Last Answer : a) LOCK# or PLOCK#

Why 8085 processor is called an 8 bit processor? a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b. Why 8085 processor is called an 8 bit processor? a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b.

Description : Why 8085 processor is called an 8 bit processor? a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b.

Last Answer : a) Because 8085 processor has 8 bit ALU.

Each memory location has: a. Address b. Contents c. Both A and B d. None of these

Description : Each memory location has: a. Address b. Contents c. Both A and B d. None of these

Last Answer : c. Both A and B

“India played a crucial role in the late 19th century world economy”. Explain. -SST 10th

Description : “India played a crucial role in the late 19th century world economy”. Explain. -SST 10th

Last Answer : (i) Britain had a trade surplus' with India. Britain used this surplus to balance its trade deficits with other countries. (ii) Britain's trade surplus in India also helped pay the so-called ... of the world. (v) India become a major market for the final goods: especially cotton textile.

“India played a crucial role in the late 19th century world economy.” Explain by giving an example. -SST 10th

Description : “India played a crucial role in the late 19th century world economy.” Explain by giving an example. -SST 10th

Last Answer : (i)Trade Surplus : Britain had a trade surplus with India, i e., a situation under which the value of exports is more than the imports. Britain used this surplus to balance its trade ... workers from Bihar. Uttar Pradesh, Central India migrated to other countries to work in mines and plantations.

Knowledge and reasoning also play a crucial role in dealing with __________________ environment. a) Completely Observable b) Partially Observable c) Neither Completely nor Partially Observable d) Only Completely and Partially Observable

Description : Knowledge and reasoning also play a crucial role in dealing with __________________ environment. a) Completely Observable b) Partially Observable c) Neither Completely nor Partially Observable d) Only Completely and Partially Observable

Last Answer : b) Partially Observable

In Tripura, which nodal agency play crucial role in organising community capacity building programmes and conducting mock drills at State, District and Block levels (a) National Disaster Response Force (b) National Informatics Centre (c) District Disaster Management Authority (d) Tripura Disaster Management Authority

Description : In Tripura, which nodal agency play crucial role in organising community capacity building programmes and conducting mock drills at State, District and Block levels (a) National Disaster ... Informatics Centre (c) District Disaster Management Authority (d) Tripura Disaster Management Authority

Last Answer : (a) National Disaster Response Force

The standard I/O is also called: a. Isolated I/O b. Parallel I/O c. both a and b d. none of these

Description : The standard I/O is also called: a. Isolated I/O b. Parallel I/O c. both a and b d. none of these

Last Answer : a. Isolated I/O