Description : The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.A.control busB.control instructionsC. address decoder D.CPU
Last Answer : C. address decoder
Description : The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus
Last Answer : a. Address bus
Description : CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : b. Data bus
Description : Which bus carry addresses: a. System bus b. Address bus c. Control bus d. Data bus
Last Answer : b. Address bus
Description : What is the control unit's function in the CPU? a. To transfer data to primary storage b. to store program instruction c. to perform logic operations d. to decode program instruction
Last Answer : b. to store program instruction
Description : System Bus Contains: a. Address Bus b. Data Bus c. Control Bus d. All of these
Last Answer : d. All of these
Description : Which of the following are the two main components of the CPU? a. Control unit and registers b. Registers and main memory c. Control Unit and ALU d. ALU and bus
Last Answer : c. Control Unit and ALU
Description : The CPU completes yields control of the bus to the DMA controller via: a. DMA acknowledge signal b. DMA integrated signal c. DMA implicitly signal d. None of these
Last Answer : a. DMA acknowledge signal
Description : The ____ place the data from a register onto the data bus: a. CPU b. ALU c. Both A and B d. None of these
Last Answer : a. CPU
Description : The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B
Last Answer : b. Write
Description : The information on the data bus is transferred to the ______register: a. MOC b. MDR c. VAM d. CPU
Last Answer : b. MDR
Description : The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use memory bus. A memory read/write employs one machine cycle. For ... (A) 500 Kbytes/sec (B) 2.2 Mbytes/sec (C) 125 Kbytes/sec (D) 250 Kbytes/sec
Last Answer : (D) 250 Kbytes/sec
Description : The external device is connected to a pin called the ______ pin on the processor chip. a. Interrupt b. Transfer c. Both d. None of these
Last Answer : a. Interrupt
Description : An error in computer data is called a. Chip b. Bug c. CPU d. Storage device
Last Answer : b. Bug
Description : CPU does not perform the operation a. data transfer b. logic operation c. arithmetic operation d. all of above
Last Answer : b. logic operation
Description : Which bus plays a crucial role in I/O: a. System bus b. Control bus c. Address bus d. Both A and B
Last Answer : b. Control bus
Description : In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode
Last Answer : c) bus width select
Last Answer : b) address valid strobe select
Description : What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width
Last Answer : c) Address bus width
Description : Which is the components of computer: a. System Bus b. CPU c. Memory Unit d. All of these
Description : Which Bus connects CPU & level 2 cache: a. Rear side bus b. Front side bus c. Memory side bus d. None of these
Last Answer : b. Front side bus
Description : _____ a subsystem that transfer data between computer components inside a computer or between computer: a. Chip b. Register c. Processor d. Bus
Last Answer : d. Bus
Description : The upper red arrow show that CPU sends out the control signals____ and _____ indicate the data is read from the memory: a. Memory request b. Read c. Both A and B d. None of these
Last Answer : c. Both A and B
Description : In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR
Last Answer : b. CPU
Description : Offline device is a. A device which is not connected to CPU b. A device which is connected to CPU c. A direct access storage device d. An I/O device
Last Answer : a. A device which is not connected to CPU
Description : A/n …. Device is any device that provides information, which is sent to the CPU a. Input b. Output c. CPU d. Memory
Last Answer : a. Input
Description : In most IBM PCs, the CPU, the device drives, memory expansion slots and active components are mounted on a single board. What is the name of this board? a. Motherboard b. Breadboard c. Daughter board d. Grandmother board
Last Answer : a. Motherboard
Description : The external system bus architecture is created using from ______ architecture: a. Pascal b. Dennis Ritchie c. Charles Babbage d. Von Neumann
Last Answer : d. Von Neumann
Description : A 32-bit address bus allows access to a memory of capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb 2.Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors
Last Answer : c) all x86 processors
Description : A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above
Description : Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these
Last Answer : a. MAR
Description : The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Fully decoding b. Half decoding c. Both a & b d. None of these
Last Answer : a. Fully decoding
Description : In linear decoding address bus of 16-bit wide can connect only ____ of RAM. a. 16 KB b. 6KB c. 12KB d. 64KB
Last Answer : b. 6KB
Description : The capacity of this chip is 1KB they are organized in the form of 1024 words with 8 bit word The what is the site of address bus: a. 8 bit b. 10 bit c. 12 bit d. 16 bit
Last Answer : b. 10 bit
Description : The processor 80386/80486 and the Pentium processor uses _____ bits address bus: a. 16 b. 32 c. 36 d. 64
Last Answer : b. 32
Description : A 16 bit address bus can generate___ addresses: a. 32767 b. 25652 c. 65536 d. none of these
Last Answer : c. 65536
Description : If ______input pin of 80386 if activated, allows address pipelining during 80386 bus cycles. a) BS16 b) NA c) PEREQ d) ADS
Last Answer : a) BS16
Description : In 8086 microprocessor , the address bus is ________ bit wide A. 12 bit B. 10 bit C. 16 bit D. 20 bit
Last Answer : In 8086 microprocessor, the address bus is 20 bit
Description : Which pin of port 3 is has an alternative function as write control signal for external data memory? a) P3.8 b) P3.3 c) P3.6 d) P3.1
Last Answer : d) P3.1
Last Answer : c) P3.6
Description : In 8051 an external interrupt 1 vector address is of ________ and causes of interrupt if ____. a) 000BH, a high to low transition on pin INT1 b) 001BH, a low to high transition on pin INT1 c) 0013H, a high to low transition on pin INT1 d) 0023H, a low to high transition on pin INT1
Last Answer : a) 000BH, a high to low transition on pin INT1
Description : Which of the following instruction perform the move accumulator to external RAM of 16bit address? a) MOV @ DPTR, A b) MOVX @ Ri, A c) MOV A, @ Ri d) MOVX @ DPTR, A
Last Answer : c) MOV A, @ Ri
Description : 8096 write-protected mode, no code can write to memory address between __. a) 2020 to 3FFFH b) 8000 to FFFFH c) 2000 to 3FFFH d) 2020 to 202FH 17. If the __ pin is ___ , then we have the option ... b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal
Last Answer : c) EA, high, external, internal
Description : The Command to access the memory or the I/O device is carried by ______ A. Address Bus B. Data Bus C. Control Bus D. None of the Above
Last Answer : C. Control Bus
Description : A bus that transfer data from one component to another or between computers is called _________ A. Address Bus B. Data Bus C. Control Bus D. None of the Above
Last Answer : B. Data Bus
Description : Which are the READ operation can in simple steps: a. Address b. Data c. Control d. All of these
Description : The brain of any computer system is a. ALU b. Memory c. CPU d. Control unit
Last Answer : c. CPU
Description : What is the responsibility of the logical unit in the CPU of a computer? a. To produce result b. To compare numbers c. To control flow of information d. To do math’s works
Last Answer : b. To compare numbers
Description : The central processing unit (CPU) consists of a. Input, output and processing b. Control unit, primary storage, and secondary storage c. Control unit, arithmetic-logic unit and primary storage d. Control unit, processing, and primary storage
Last Answer : c. Control unit, arithmetic-logic unit and primary storage