Description : Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU: a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : a. Control bus
Description : A 16 bit address bus can generate___ addresses: a. 32767 b. 25652 c. 65536 d. none of these
Last Answer : c. 65536
Description : System Bus Contains: a. Address Bus b. Data Bus c. Control Bus d. All of these
Last Answer : d. All of these
Description : The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus
Last Answer : a. Address bus
Description : The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.A.control busB.control instructionsC. address decoder D.CPU
Last Answer : C. address decoder
Description : CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : b. Data bus
Description : Which bus plays a crucial role in I/O: a. System bus b. Control bus c. Address bus d. Both A and B
Last Answer : b. Control bus
Description : In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode
Last Answer : c) bus width select
Last Answer : b) address valid strobe select
Description : What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width
Last Answer : c) Address bus width
Description : If in a computer, 16 bits are used to specify address in a RAM, the number of addresses will be a. 216 b. 65,536 c. 64K d. Any of the above
Last Answer : b. 65,536
Description : Which of the following statements on DRAM are correct? i) Page mode read operation is faster than RAS read. ii) RAS input remains active during column address strobe. iii) The row and column addresses are strobed into the ... RAS and CAS inputs respectively. a) i & iii b) i & ii c) all d) iii
Last Answer : d) iii
Description : A 32-bit address bus allows access to a memory of capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb 2.Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors
Last Answer : c) all x86 processors
Description : A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above
Last Answer : b. Address bus
Description : Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these
Last Answer : a. MAR
Description : The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Fully decoding b. Half decoding c. Both a & b d. None of these
Last Answer : a. Fully decoding
Description : In linear decoding address bus of 16-bit wide can connect only ____ of RAM. a. 16 KB b. 6KB c. 12KB d. 64KB
Last Answer : b. 6KB
Description : The capacity of this chip is 1KB they are organized in the form of 1024 words with 8 bit word The what is the site of address bus: a. 8 bit b. 10 bit c. 12 bit d. 16 bit
Last Answer : b. 10 bit
Description : The processor 80386/80486 and the Pentium processor uses _____ bits address bus: a. 16 b. 32 c. 36 d. 64
Last Answer : b. 32
Description : If ______input pin of 80386 if activated, allows address pipelining during 80386 bus cycles. a) BS16 b) NA c) PEREQ d) ADS
Last Answer : a) BS16
Description : In 8086 microprocessor , the address bus is ________ bit wide A. 12 bit B. 10 bit C. 16 bit D. 20 bit
Last Answer : In 8086 microprocessor, the address bus isĀ 20 bit
Description : A set of register which contain are: a. data b. memory addresses c. result d. all of these
Last Answer : d. all of these
Description : Which are the READ operation can in simple steps: a. Address b. Data c. Control d. All of these
Description : What type of control pins are needed in a microprocessor to regulate traffic on the bus, in order to prevent two devices from trying to use it at the same time? a. Bus control b. Interrupts c. Bus arbitration d. Status
Last Answer : c. Bus arbitration
Description : Which of the following is used for manufacturing chips? a. Control bus b. Control unit c. Parity unit d. Semiconductor
Last Answer : d. Semiconductor
Description : Which is used for manufacturing chips? a. Bus b. Control unit c. Semiconductors d. A and b only
Last Answer : c. Semiconductors
Description : Which of the following are the two main components of the CPU? a. Control unit and registers b. Registers and main memory c. Control Unit and ALU d. ALU and bus
Last Answer : c. Control Unit and ALU
Description : The CPU completes yields control of the bus to the DMA controller via: a. DMA acknowledge signal b. DMA integrated signal c. DMA implicitly signal d. None of these
Last Answer : a. DMA acknowledge signal
Description : Which is not the control bus signal: a. READ b. WRITE c. RESET
Last Answer : c. RESET
Description : The ____ place the data from a register onto the data bus: a. CPU b. ALU c. Both A and B d. None of these
Last Answer : a. CPU
Description : The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B
Last Answer : b. Write
Description : The information on the data bus is transferred to the ______register: a. MOC b. MDR c. VAM d. CPU
Last Answer : b. MDR
Description : _____ a subsystem that transfer data between computer components inside a computer or between computer: a. Chip b. Register c. Processor d. Bus
Last Answer : d. Bus
Description : Why 8085 processor is called an 8 bit processor? a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b.
Last Answer : a) Because 8085 processor has 8 bit ALU.
Description : Using 12 binary digits how many unique house addresses would be possible: a. 28=256 b. 212=4096 c. 216=65536 d. None of these
Last Answer : b. 212=4096
Description : The area of memory with addresses near zero are called: a. High memory b. Mid memory c. Memory d. Low memory
Last Answer : d. Low memory
Description : Addresses in control memory is made by for each register group: a. Address select logic b. Data select logic c. Control select logic d. All of these
Last Answer : a. Address select logic
Description : The point where control returns after a subprogram is completed is known as the : a. Return address b. Main Address c. Program Address d. Current Address
Last Answer : a. Return address
Description : When the RET instruction at the end of subroutine is executed, a. the information where the stack is iniatialized is transferred to the stack pointer b. the memory address of the RET instruction is ... two data bytes stored in the top two locations of the stack are transferred to the stack pointer
Last Answer : c. two data bytes stored in the top two locations of the stack are transferred to the program counter
Description : Which of the following registers is used to keep track of address of the memory location where the next instruction is located? a. Memory Address Register b. Memory Data Register c. Instruction Register d. Program Register
Last Answer : d. Program Register
Description : Which of the following registers is used to keep track of address of the memory location where the next instruction is located? a. Memory address register b. Memory data register c. Instruction register d. Program counter
Last Answer : d. Program counter
Description : Which of the following registers is loaded with the contents of the memory location pointed by the PC? a. Memory address register b. Memory data register c. Instruction registers d. Program counter
Last Answer : c. Instruction registers
Description : A storage area used to store data to a compensate for the difference in speed at which the different units can handle data is a. Memory b. Buffer c. Accumulator d. Address
Last Answer : b. Buffer
Description : Which of the following will happen when data is entered into a memory location? a. It will add to the content of the location b. It will change the address of the memory location c. It will erase the previous content d. It will not be fruitful if there is already some data at the location
Last Answer : c. It will erase the previous content
Description : Which of the following registers is loaded with the contents of the memory location pointed by the PC? a. Memory address registers b. Memory data registers c. Instruction register d. Program counter
Last Answer : c. Instruction register
Description : 8088 microprocessor differs with 8086 microprocessor in a) Data width on the output b) Address capability c) Support of coprocessor d) Support of MAX / MIN mode
Last Answer : a) Data width on the output
Description : Which is the components of computer: a. System Bus b. CPU c. Memory Unit d. All of these
Description : The external system bus architecture is created using from ______ architecture: a. Pascal b. Dennis Ritchie c. Charles Babbage d. Von Neumann
Last Answer : d. Von Neumann
Description : Dot-matrix is a type of a. Tape e. Printer f. Disk g. Bus
Last Answer : e. Printer