Description : Which technique is used for main memory array design: a. Linear decoding b. Fully decoding c. Both A and B d. None of these
Last Answer : c. Both A and B
Description : Which storage technique dose not decoding circuit: a. Linear decoding b. Fully decoding c. Partially d. None of these
Last Answer : a. Linear decoding
Description : In linear decoding address bus of 16-bit wide can connect only ____ of RAM. a. 16 KB b. 6KB c. 12KB d. 64KB
Last Answer : b. 6KB
Description : Which statement is wrong according to linear decoding : a. Address map is not contiguous. b. Confects occur if two of the select lines become active at the same time c. If all unused address lines are not used as chip selectors then these unused lines become don’t cares d. None of these
Last Answer : d. None of these
Description : CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : b. Data bus
Description : Which bus plays a crucial role in I/O: a. System bus b. Control bus c. Address bus d. Both A and B
Last Answer : b. Control bus
Description : Pipelining strategy is called implement a. instruction execution b. instruction prefetch c. instruction decoding d. instruction manipulation
Last Answer : b. instruction prefetch
Description : The work of EU is ________ A. encoding B. decoding C. processing D. calculations
Last Answer : The work of EU is decoding
Description : System Bus Contains: a. Address Bus b. Data Bus c. Control Bus d. All of these
Last Answer : d. All of these
Description : The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.A.control busB.control instructionsC. address decoder D.CPU
Last Answer : C. address decoder
Description : A 32-bit address bus allows access to a memory of capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb 2.Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors
Last Answer : c) all x86 processors
Description : A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above
Last Answer : b. Address bus
Description : The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus
Last Answer : a. Address bus
Description : Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these
Last Answer : a. MAR
Description : The capacity of this chip is 1KB they are organized in the form of 1024 words with 8 bit word The what is the site of address bus: a. 8 bit b. 10 bit c. 12 bit d. 16 bit
Last Answer : b. 10 bit
Description : Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU: a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : a. Control bus
Description : The processor 80386/80486 and the Pentium processor uses _____ bits address bus: a. 16 b. 32 c. 36 d. 64
Last Answer : b. 32
Description : A 16 bit address bus can generate___ addresses: a. 32767 b. 25652 c. 65536 d. none of these
Last Answer : c. 65536
Description : Which bus carry addresses: a. System bus b. Address bus c. Control bus d. Data bus
Description : If ______input pin of 80386 if activated, allows address pipelining during 80386 bus cycles. a) BS16 b) NA c) PEREQ d) ADS
Last Answer : a) BS16
Description : In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode
Last Answer : c) bus width select
Last Answer : b) address valid strobe select
Description : What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width
Last Answer : c) Address bus width
Description : In 8086 microprocessor , the address bus is ________ bit wide A. 12 bit B. 10 bit C. 16 bit D. 20 bit
Last Answer : In 8086 microprocessor, the address bus is 20 bit
Description : The external system bus architecture is created using from ______ architecture: a. Pascal b. Dennis Ritchie c. Charles Babbage d. Von Neumann
Last Answer : d. Von Neumann
Description : Normally Z bus matrix is a a) null matrix b) sparse matrix c) full matrix d) unit matrix
Last Answer : full matrix
Description : Select the TRUE statement. A)Wholesaling activities must be performed during distribution of all goods, whether or not a wholesaling institution is involved. B)Only wholesaling establishments ... )The biggest problem with the wholesaling process is that inefficient wholesalers are not eliminated.
Last Answer : A)Wholesaling activities must be performed during distribution of all goods, whether or not a wholesaling institution is involved.
Description : Which Bus connects CPU & level 2 cache: a. Rear side bus b. Front side bus c. Memory side bus d. None of these
Last Answer : b. Front side bus
Description : Why 8085 processor is called an 8 bit processor? a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b.
Last Answer : a) Because 8085 processor has 8 bit ALU.
Description : The ____ place the data from a register onto the data bus: a. CPU b. ALU c. Both A and B d. None of these
Last Answer : a. CPU
Description : The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B
Last Answer : b. Write
Description : The network of wires or electronic path ways on mother board back side: a. PCB b. BUS c. BOTH A and B d. None of these
Last Answer : c. BOTH A and B
Description : Which of the following statements on DRAM are correct? i) Page mode read operation is faster than RAS read. ii) RAS input remains active during column address strobe. iii) The row and column addresses are strobed into the ... RAS and CAS inputs respectively. a) i & iii b) i & ii c) all d) iii
Last Answer : d) iii
Description : ______ input is available, so that another coprocessor can be connected and function in _________ with the 8087. . a) RQ/GT0, parallel b) RQ/GT1, parallel c) QS1 & QS0, parallel d) S0 & S1, parallel.
Last Answer : a) RQ/GT0, parallel
Description : RIM is used to check whether, ______ a) The write operation is done or not b) The interrupt is Masked or not c) a & b
Last Answer : b) The interrupt is Masked or not
Description : Opcode is the machine instruction obtained from decoding instruction stored in. a. Stack pointer b. Address pointer Cc. Instruction register d. Incrementer
Last Answer : Cc. Instruction register
Description : In one corner of its magazine advertisement for office copiers, Pitney Bowes places a small box asking for the names and addresses of individuals or companies seeking more information. Pitney has ... facilitate ______ for this communication. A)decoding. B)feedback. C)encoding. D)noise reduction.
Last Answer : D)noise reduction.
Description : What type of control pins are needed in a microprocessor to regulate traffic on the bus, in order to prevent two devices from trying to use it at the same time? a. Bus control b. Interrupts c. Bus arbitration d. Status
Last Answer : c. Bus arbitration
Description : Which is the components of computer: a. System Bus b. CPU c. Memory Unit d. All of these
Description : Which of the following is used for manufacturing chips? a. Control bus b. Control unit c. Parity unit d. Semiconductor
Last Answer : d. Semiconductor
Description : Which is used for manufacturing chips? a. Bus b. Control unit c. Semiconductors d. A and b only
Last Answer : c. Semiconductors
Description : Dot-matrix is a type of a. Tape e. Printer f. Disk g. Bus
Last Answer : e. Printer
Description : Which of the following are the two main components of the CPU? a. Control unit and registers b. Registers and main memory c. Control Unit and ALU d. ALU and bus
Last Answer : c. Control Unit and ALU
Description : The CPU completes yields control of the bus to the DMA controller via: a. DMA acknowledge signal b. DMA integrated signal c. DMA implicitly signal d. None of these
Last Answer : a. DMA acknowledge signal
Description : The information on the data bus is transferred to the ______register: a. MOC b. MDR c. VAM d. CPU
Last Answer : b. MDR
Description : Which is not the control bus signal: a. READ b. WRITE c. RESET
Last Answer : c. RESET
Description : Which is called superhighway: a. Processor b. Multiplexer c. Backbone bus d. None of these
Last Answer : c. Backbone bus
Description : _____ a subsystem that transfer data between computer components inside a computer or between computer: a. Chip b. Register c. Processor d. Bus
Last Answer : d. Bus
Description : To prevent another master from taking over the bus during a critical operation, the 486 can assert its _____signal. a) LOCK# or PLOCK# b) HOLD or BOFF c) HLDA d) HOLD
Last Answer : a) LOCK# or PLOCK#
Description : Each memory location has: a. Address b. Contents c. Both A and B d. None of these