In a positive-edge-triggered JK flip-flop, if J and K both are high then the output will be ............. on the rising edge of the clock. (A) No change (B) Set (C) Reset (D) Toggle

In a positive-edge-triggered JK flip-flop, if J and K both are high then the output will be ............. on the rising edge of the clock. (A) No change (B) Set (C) Reset (D) Toggle
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1 Answer

Answer :

(D) Toggle 
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In a positive edge triggered JK flip-flop, J = 1, K = 0 and clock pulse is rising, Q will be

Description : In a positive edge triggered JK flip-flop, J = 1, K = 0 and clock pulse is rising, Q will be (a) 0 (b) 1 (c) showing no change (d) toggle 

Last Answer : In a positive edge triggered JK flip-flop, J =1, K= 0 and clock pulse is rising, a Q will be 1

For JK flip flop with J=1, K=0, the output after clock pulse will be (A) 0. (B) 1. (C) high impedance. (D) no change.

Description : For JK flip flop with J=1, K=0, the output after clock pulse will be (A) 0. (B) 1. (C) high impedance. (D) no change.

Last Answer : (B) 1.

The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in figure is 10 KHZ.

Description : The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in figure is 10 KHZ. The frequency of the signal at Q is A) 10 KHz B) 2.5 KHz C) 20 KHz D) 5 KHz

Last Answer : The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in figure is 10 KHZ. The frequency of the signal at Q is 5 KHz

The MSI chip 7474 is (A) Dual edge triggered JK flip-flop (TTL). (B) Dual edge triggered D flip-flop (CMOS). (C) Dual edge triggered D flip-flop (TTL). (D) Dual edge triggered JK flip-flop (CMOS).

Description : The MSI chip 7474 is (A) Dual edge triggered JK flip-flop (TTL). (B) Dual edge triggered D flip-flop (CMOS). (C) Dual edge triggered D flip-flop (TTL). (D) Dual edge triggered JK flip-flop (CMOS).

Last Answer : Ans: C MSI chip 7474 dual edge triggered D Flip-Flop.

Read the following statements: i. Gate is a combinational logic. ii. JK Flip-flop in toggle mode is not

Description : Read the following statements: i. Gate is a combinational logic. ii. JK Flip-flop in toggle mode is not combinational logic. iii. MSJK Flip-flop suffers from race-around. iv. Counters are sequential circuits. Which choice is correct? (A) i, ii (B) i, ii, iv (C) ii, iii, iv (D) i, ii, iii

Last Answer : Read the following statements: i. Gate is a combinational logic. ii. JK Flip-flop in toggle mode is not combinational logic. iii. MSJK Flip-flop suffers from race-around. iv. Counters are sequential circuits. Which choice is ... (A) i, ii (B) i, ii, iv (C) ii, iii, iv (D) i, ii, iii

Register are assumed to use positive-edge-triggered _ a. Flip-flop b. Logics Cc. Circuit d. Operation

Description : Register are assumed to use positive-edge-triggered _ a. Flip-flop b. Logics Cc. Circuit d. Operation

Last Answer : a. Flip-flop

Which of the following describes the operation of a positive edge - triggered D -type flip-flop?

Description : Which of the following describes the operation of a positive edge - triggered D -type flip-flop? a) if both inputs are HIGH, the output will toggle b) the output will follow the input on the leading ... on the leading edge of the clock and is passed to the output on the trailing edge of the clock.

Last Answer : Which of the following describes the operation of a positive edge - triggered D -type flip-flop?   the output will follow the input on the leading edge of the clock

A J -K flip-flop with J= 1 and K= 1 has a 20 kHz clock input. The Q output is :

Description :  A J -K flip-flop with J= 1 and K= 1 has a 20 kHz clock input. The Q output is : (A) Constant and low (B) Constant and high (C) A square wave with 20 kHz frequency (D) A square wave with 10 kHz frequency

Last Answer : a

Which of the following flip-flops is free from race condition ? (A) T flip-flop (B) SR flip-flop (C) Master-slave JK flip-flop (D) None of the above

Description : Which of the following flip-flops is free from race condition ? (A) T flip-flop (B) SR flip-flop (C) Master-slave JK flip-flop (D) None of the above

Last Answer : (C) Master-slave JK flip-flop

For JK flipflop J = 0, K=1, the output after clock pulse will be (A) 1. (B) no change. (C) 0. (D) high impedance.

Description : For JK flipflop J = 0, K=1, the output after clock pulse will be (A) 1. (B) no change. (C) 0. (D) high impedance.

Last Answer : Ans: C J=0, K=1, these inputs will reset the flip-flop after the clock pulse. So whatever be the previous output, the next state will be 0.

What is edge-triggered flip-flop?

Description : What is edge-triggered flip-flop?

Last Answer : The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive ... negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock.

What is edge-triggered flip-flop?

Description : What is edge-triggered flip-flop?

Last Answer : The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock.

The output of a JK flip-flop with asynchronous preset and clear inputs is ‘1’. The output can be changed to ‘0’

Description : The output of a JK flip-flop with asynchronous preset and clear inputs is ‘1’. The output can be changed to ‘0’ with one of the following conditions by applying A) J = 0, K = 0 and using a clock B) J = 1, K = 0 and using the clock C) Asynchronous preset input D) J = 1, K = 1 and using the clock 

Last Answer : The output of a JK flip-flop with asynchronous preset and clear inputs is ‘1’. The output can be changed to ‘0’ with one of the following conditions by applying J = 1, K = 1 and using the clock 

The output of a JK flipflop with asynchronous preset and clear inputs is ‘1’. The output can be changed to ‘0’ with one of the following conditions. (A) By applying J = 0, K = 0 and using a clock. (B) By applying J = 1, K = 0 and using the clock. (C) By applying J = 1, K = 1 and using the clock. (D) By applying a synchronous preset input.

Description : The output of a JK flipflop with asynchronous preset and clear inputs is 1'. The output can be changed to 0' with one of the following conditions. (A) By applying J = 0, K = 0 and using a clock. (B) ... (C) By applying J = 1, K = 1 and using the clock. (D) By applying a synchronous preset input.

Last Answer : Ans: C Preset state of JK Flip-Flop =1 With J=1 K=1 and the clock next state will be complement of the present state.

Which Flip Flop is used to store data in registers? (A) D Flip Flop (B) JK Flip Flop (C) RS Flip Flop (D) None of the Above

Description : Which Flip Flop is used to store data in registers? (A) D Flip Flop (B) JK Flip Flop (C) RS Flip Flop (D) None of the Above

Last Answer : (A) D Flip Flop

What is the operation of JK flip-flop?

Description : What is the operation of JK flip-flop?

Last Answer : When K input is low and J input is high the Q output of flip-flop is set. When K input is high and J input is low the Q output of flip-flop is reset. When both the inputs ... are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.

What is the operation of JK flip-flop?

Description : What is the operation of JK flip-flop?

Last Answer : When K input is low and J input is high the Q output of flip-flop is set. When K input is high and J input is low the Q output of flip-flop is reset. When both the inputs K and ... are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.

What is race around condition in JK flip flop and how it can be eliminated?

Description : What is race around condition in JK flip flop and how it can be eliminated?

Last Answer : For the racing around to take place, it is necessary to have the enable input high along with J=K=1. As the enable input remains high for a long time in a JK latch, the problem of ... to zero. Hence the multiple toggling cannot take place. Thus the edge triggering avoids the race around condition.

In a JK flip-flop, for what input next state is complement of the present state

Description : In a JK flip-flop, for what input next state is complement of the present state (A)J=0,K=0 (B)J=1,K=0 (C)J=0,K=1 (D)J=1,K=1

Last Answer : In a JK flip-flop, for what input next state is complement of the present state (A)J=0,K=0 (B)J=1,K=0 (C)J=0,K=1 (D)J=1,K=1

If a voltage (positive or negative) is measured on the "1" output of a flip-flop, what state is it in?

Description : If a voltage (positive or negative) is measured on the "1" output of a flip-flop, what state is it in?

Last Answer : SET state.

The output of SR flip flop when S=1, R=0 is (A) 1 (B) 0 (C) No change (D) High impedance

Description : The output of SR flip flop when S=1, R=0 is (A) 1 (B) 0 (C) No change (D) High impedance

Last Answer : Ans: A As for the SR flip-flop S=set input R=reset input ,when S=1, R=0, Flip-flop will be set.

State functions of preset, clear, clock and SR inputs related to SR flip flop.

Description : State functions of preset, clear, clock and SR inputs related to SR flip flop.

Last Answer : Preset Input: is an asynchronous input to set the Q output to 1 Clear Input: is also asynchronous input to reset the Q output to 0 Clock Input: is used to input external logic clock pulse (HIGH-LO) to ... set the Q output. And R is the reset input which is used to reset Q output of the flipflop.

Each flip-flop in a 4-bit ripple counter introduces a maximum delay of 40 n sec. The maximum clock frequency

Description : Each flip-flop in a 4-bit ripple counter introduces a maximum delay of 40 n sec. The maximum clock frequency is (a) 2.65 MHz (b) 6.25 MHz (c) 5.26 MHz (d) 6.52 MHz 

Last Answer : Each flip-flop in a 4-bit ripple counter introduces a maximum delay of 40 ns. The maximum clock frequency is 6.25MHz. nff  * Tdelay = 4*40 =160ns so, max. frequency = 1/ (200*10-9 ) = 6.25MHz          

Consider an undirected graph G where self-loops are not allowed. The vertex set of G is {(i, j) | 1 ≤ i ≤ 12, 1 ≤ j ≤ 12}. There is an edge between (a, b) and (c, d) if |a – c| ≤ 1 or |b–d| ≤ 1. The number of edges in this graph is (A) 726 (B) 796 (C) 506 (D) 616

Description : Consider an undirected graph G where self-loops are not allowed. The vertex set of G is {(i, j) | 1 ≤ i ≤ 12, 1 ≤ j ≤ 12}. There is an edge between (a, b) and (c, d) if |a – c| ≤ 1 or |b–d| ≤ 1. The number of edges in this graph is (A) 726 (B) 796 (C) 506 (D) 616

Last Answer : (D) 616

The bits are shifted and the first flip-flop receives its binary information from the____ a. Serial output b. Serial input c. Both d. None

Description : The bits are shifted and the first flip-flop receives its binary information from the____ a. Serial output b. Serial input c. Both d. None

Last Answer : b. Serial input

In which computers, the binary number are represented by a set of binary storage device such as flip flop: a. Microcomputer b. Personal computer c. Digital computer

Description : In which computers, the binary number are represented by a set of binary storage device such as flip flop: a. Microcomputer b. Personal computer c. Digital computer

Last Answer : c. Digital computer

A, what logic element enables FF3 to toggle with the clock?

Description : A, what logic element enables FF3 to toggle with the clock?

Last Answer : The AND gate

Assume that K goes HIGH and J goes LOW; when will the FF reset?

Description : Assume that K goes HIGH and J goes LOW; when will the FF reset?

Last Answer : When the clock pulse goes LOW.

Keeping in view the ‘fluid mosaic model’ for the structure of cell membrane, which one of the following statement is correct with respect to the movements of lipids and proteins from one lipid monolayer to the other (described as flip-flop movement)?(a) While proteins can flip-flop, lipids can not (b) Neither lipids, nor proteins can flip-flop (c) Both lipids and proteins can flip-flop (d) While lipids can rarely flip-flop, proteins cannot.

Description : Keeping in view the fluid mosaic model' for the structure of cell membrane, which one of the following statement is correct with respect to the movements of lipids and proteins from one lipid ... ) Both lipids and proteins can flip-flop (d) While lipids can rarely flip-flop, proteins cannot.

Last Answer : (d) While lipids can rarely flip-flop, proteins cannot.

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Description : SOD pin can drive a D flip-flop? a) SOD cannot drive any flip-flops. b) SOD cannot drive D flip-flop, but can drive any other flop-flops. c) Yes, SOD can drive D flop-flop. d) No, SOD cannot drive any other flop-flops except D flop-flop

Last Answer : b) SOD cannot drive D flip-flop, but can drive any other flop-flops

The ……….. is code that recognizes some special sequence of input or is triggered by being run from a certain user ID of by unlikely sequence of events. A) Trap doors B) Trojan horse C) Logic Bomb D) Virus

Description : The ……….. is code that recognizes some special sequence of input or is triggered by being run from a certain user ID of by unlikely sequence of events. A) Trap doors B) Trojan horse C) Logic Bomb D) Virus

Last Answer : A) Trap doors

What will be the output of Q if J is HIGH, PS and CLR are HIGH, and the clock is going negative?

Description : What will be the output of Q if J is HIGH, PS and CLR are HIGH, and the clock is going negative?

Last Answer : Set, or HIGH (1).

I had a great uncle who said a 'flip-flop' was an old slang word for a radio. Has anyone else ever heard this?

Description : I had a great uncle who said a 'flip-flop' was an old slang word for a radio. Has anyone else ever heard this?

Last Answer : I never heard of that. I’m 67.

When I look at her, my heart does a flip-flop. Why?

Description : When I look at her, my heart does a flip-flop. Why?

Last Answer : JP Must be a case of puppy love. You made me stop and look at the picture of my two goldens that I keep on my desk. I lost them a few years ago. Enjoy every minute of your time with her.

Is the flip flop sandals on guys a fad or is it here to stay?

Description : Is the flip flop sandals on guys a fad or is it here to stay?

Last Answer : They are here to stay. I don't wear them because I'm desperate to fit in. I wear them because I like air on my feet. I'm also used to colder temperatures, so it's not a big deal to wear them ... better because there is colder air on my feet and they are easy to slip on if I have to run out quickly.

What is SR flip-flop ?

Description : What is SR flip-flop ?

Last Answer : SR Flip-flop is the simplest flip flop. The full form of SR is - Set Reset . In SR flip-flop, setting the output state to 1 or HIGH is called SET and 0 or LOW is called RESET . SR flip- ... formed by connecting two NAND gates or NOR gates and connecting the input of one to the output of the other .

How many flip flop are required to store the binary value of 1101?

Description : How many flip flop are required to store the binary value of 1101?

Last Answer : What is the answer ?

15 things you never knew about tarek and christina from flip or flop?

Description : 15 things you never knew about tarek and christina from flip or flop?

Last Answer : Answer written by Urbo.com in March 21 2016It all started as an office romance.Tarek and Christina met at a real estate office. "We started our relationship working together," Christina said. Was it ... Scott's "Brother vs. Brother." What impromptu HGTV appearances are in store for them this year?

What's That Flip Flop Feeling My Heart Is Making?

Description : What's That Flip Flop Feeling My Heart Is Making?

Last Answer : A heart arrhythmia can be a life-threatening situation and requires medical attention. If you suffer with this heart condition chances are that you have already been counseled on avoiding stimulants. ... this activity will bring the heart back under control until medical attention can be consulted.

In a computer is capable to store single binary bit. A) Capacitor B) Flip flop C) Register D) Inductor

Description : In a computer is capable to store single binary bit. A) Capacitor B) Flip flop C) Register D) Inductor

Last Answer : Answer : B

Which of the following features is predicted by the Nicolson–Singer fluid mosaic model of biological membranes? (A) Membrane lipids do not diffuse laterally (B) Membrane lipid is primarily in a monolayer form (C) Membrane lipids freely flip-flop (D) Membrane proteins may diffuse laterally

Description : Which of the following features is predicted by the Nicolson–Singer fluid mosaic model of biological membranes? (A) Membrane lipids do not diffuse laterally (B) Membrane lipid is primarily in a monolayer form (C) Membrane lipids freely flip-flop (D) Membrane proteins may diffuse laterally

Last Answer : Answer : D

Which of the following is not a magnetic memory: a) Flip-flop b) Tape c) Drum d) Disk

Description : Which of the following is not a magnetic memory: a) Flip-flop b) Tape c) Drum d) Disk

Last Answer : Ans: A

The circuit used to store one bit of data is known as_____ A. Encoder B. OR C. Flip Flop D. None of the Above

Description : The circuit used to store one bit of data is known as_____ A. Encoder B. OR C. Flip Flop D. None of the Above

Last Answer : C. Flip Flop

The schematic diagram shown in the illustration represents which of the listed solid-state circuits? EL-0069 A. Bridge rectifier B. Magnetic amplifier C. Flip-flop generator D. Cathodic amplifier

Description : The schematic diagram shown in the illustration represents which of the listed solid-state circuits? EL-0069 A. Bridge rectifier B. Magnetic amplifier C. Flip-flop generator D. Cathodic amplifier

Last Answer : Answer: A

What is a master-slave flip-flop?

Description : What is a master-slave flip-flop?

Last Answer : A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.

What is the operation of T flip-flop?

Description : What is the operation of T flip-flop?

Last Answer : T flip-flop is also known as Toggle flip-flop. • When T=0 there is no change in the output. • When T=1 the output switch to the complement state (ie) the output toggles.

What is the operation of D flip-flop?

Description : What is the operation of D flip-flop?

Last Answer : In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.

What are the different types of flip-flop?

Description : What are the different types of flip-flop?

Last Answer : There are various types of flip flops. Some of them are mentioned below they are, RS flip-flop SR flip-flop D flip-flop JK flip-flop T flip-flop

Define Flip flop.

Description : Define Flip flop.

Last Answer : The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state.

According to widely accepted “fluid mosaic model” cell membranes are semi-fluid, where lipids and integral proteins can diffuse randomly. In recent years, this model has been modified in several respects. In this regard, which of the following statements is incorrect? (a) Proteins in cell membranes can travel within the lipid bilayer. (b) Proteins can also undergo flip-flop movements in the lipid bilayer. (c) Proteins can remain confined within certain domains of the membrane.(d) Many proteins remain completely embedded within the lipid bilayer.

Description : According to widely accepted fluid mosaic model cell membranes are semi-fluid, where lipids and integral proteins can diffuse randomly. In recent years, this model has been modified in several ... domains of the membrane. (d) Many proteins remain completely embedded within the lipid bilayer.

Last Answer : (b) Proteins can also undergo flip-flop movements in the lipid bilayer.