The output of a JK flipflop with asynchronous preset and clear inputs is ‘1’. The output can be
changed to ‘0’ with one of the following conditions.
(A) By applying J = 0, K = 0 and using a clock.
(B) By applying J = 1, K = 0 and using the clock.
(C) By applying J = 1, K = 1 and using the clock.
(D) By applying a synchronous preset input.

1 Answer

Answer :

Ans: C
Preset state of JK Flip-Flop =1
With J=1 K=1 and the clock next state will be complement of the present state.

Related questions

Description : For JK flipflop J = 0, K=1, the output after clock pulse will be (A) 1. (B) no change. (C) 0. (D) high impedance.

Last Answer : Ans: C J=0, K=1, these inputs will reset the flip-flop after the clock pulse. So whatever be the previous output, the next state will be 0.

Description : The output of a JK flip-flop with asynchronous preset and clear inputs is ‘1’. The output can be changed to ‘0’ with one of the following conditions by applying A) J = 0, K = 0 and using a clock B) J = 1, K = 0 and using the clock C) Asynchronous preset input D) J = 1, K = 1 and using the clock 

Last Answer : The output of a JK flip-flop with asynchronous preset and clear inputs is ‘1’. The output can be changed to ‘0’ with one of the following conditions by applying J = 1, K = 1 and using the clock 

Description : For JK flip flop with J=1, K=0, the output after clock pulse will be (A) 0. (B) 1. (C) high impedance. (D) no change.

Last Answer : (B) 1.

Description : If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is (A) 1000 Hz (B) 500 Hz (C) 333 Hz (D) 12.5 Hz.

Last Answer : (D) 12.5 Hz.

Description : State functions of preset, clear, clock and SR inputs related to SR flip flop.

Last Answer : Preset Input: is an asynchronous input to set the Q output to 1 Clear Input: is also asynchronous input to reset the Q output to 0 Clock Input: is used to input external logic clock pulse (HIGH-LO) to ... set the Q output. And R is the reset input which is used to reset Q output of the flipflop.

Description : In a positive-edge-triggered JK flip-flop, if J and K both are high then the output will be ............. on the rising edge of the clock. (A) No change (B) Set (C) Reset (D) Toggle

Last Answer : (D) Toggle 

Description : In a positive edge triggered JK flip-flop, J = 1, K = 0 and clock pulse is rising, Q will be (a) 0 (b) 1 (c) showing no change (d) toggle 

Last Answer : In a positive edge triggered JK flip-flop, J =1, K= 0 and clock pulse is rising, a Q will be 1

Description : The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either (A) a NAND or an EX-OR (B) an OR or an EX-NOR (C) an AND or an EX-OR (D) a NOR or an EX-NOR

Last Answer : (D) a NOR or an EX-NOR

Description : What is Race Around Condition in a JK FlipFlop?

Last Answer : Ans-IN J-K FF , The clock time is higher than the output toggling time then for J=1 & K=1 , the output will be changed irrelavent of our input. This condition is known as "RACE AROUND CONDITION"..

Description : A full adder logic circuit will have (A) Two inputs and one output. (B) Three inputs and three outputs. (C) Two inputs and two outputs. (D) Three inputs and two outputs.

Last Answer : Ans: D A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there.

Description : The NOR gate output will be low if the two inputs are (A) 00 (B) 01 (C) 10 (D) 11

Last Answer : A

Description : The NAND gate output will be low if the two inputs are (A) 00 (B) 01 (C) 10 (D) 11

Last Answer : (D) 11

Description : What is the operation of JK flip-flop?

Last Answer : When K input is low and J input is high the Q output of flip-flop is set. When K input is high and J input is low the Q output of flip-flop is reset. When both the inputs ... are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.

Description : The MSI chip 7474 is (A) Dual edge triggered JK flip-flop (TTL). (B) Dual edge triggered D flip-flop (CMOS). (C) Dual edge triggered D flip-flop (TTL). (D) Dual edge triggered JK flip-flop (CMOS).

Last Answer : Ans: C MSI chip 7474 dual edge triggered D Flip-Flop.

Description :  A J -K flip-flop with J= 1 and K= 1 has a 20 kHz clock input. The Q output is : (A) Constant and low (B) Constant and high (C) A square wave with 20 kHz frequency (D) A square wave with 10 kHz frequency

Last Answer : a

Description : When the set of input data to an even parity generator is 0111, the output will be (A) 1 (B) 0 (C) Unpredictable (D) Depends on the previous input

Last Answer : Ans: B In even parity generator if number of 1 is odd then output will be zero.

Description : Define Asynchronous sequential circuit?

Last Answer : In asynchronous sequential circuits change in input signals can affect memory element at any instant of time.

Description : When an input signal A=11001 is applied to a NOT gate serially, its output signal is (A) 00111. (B) 00110. (C) 10101. (D) 11001.

Last Answer : When an input signal A=01001 is applied to a NOT gate serially , it's output signal is

Description : In successive-approximation A/D converter, offset voltage equal to 1/2 LSB is added to the D/A converter's output. This is done to (A) Improve the speed of operation. (B) Reduce the maximum ... Increase the number of bits at the output. (D) Increase the range of input voltage that can be converted

Last Answer : (B) Reduce the maximum quantization error.

Description : Design a asynchronous sequential circuit with 2 inputs T and C. The output attains a value of 1 when T = 1 & c moves from 1 to 0. Otherwise the output is 0

Last Answer : • Obtain the state diagram • Obtain the flow table • Using implication table reduce the flow table • Using merger graph obtain maximal compatibles • Verify closed & covered conditions • Plot the reduced flow table • Obtain transition table • Excitation table • Logic diagram

Description : Synchronous modems cost more than asynchronous modem because _______. A. They have larger bandwidth B. They are larger C. The production volume is larger D. They have clock recovery circuits

Last Answer : D. They have clock recovery circuits

Description : The synchronous modems are more costly than the asynchronous modems because a. they produce large volume of data b. they contain clock recovery circuits c. they transmit the data with stop and start bits d. they operate with a larger bandwidth e. none of above

Last Answer : they contain clock recovery circuits

Description : The synchronous modems are more costly than the asynchronous modemsbecause A. they produce largevolumeof data B. they contain clock recovery circuits C. they transmit thedata with stop and start bits. D. they operate witha largerbandwidth E. None of the above

Last Answer : they contain clock recovery circuits

Description : One method of troubleshooting digital circuits in a console is to ___________. A. supply alternate logic levels at the input(s) and test for change of state conditions at the output B. ground all ... output D. vary each input smoothly from 0-10 volts and test for similar variance at the output

Last Answer : Answer: A

Description : Data can be changed from special code to temporal code by using (A) Shift registers (B) counters (C) Combinational circuits (D) A/D converters.

Last Answer : Ans: A Data can be changed from special code to temporal code by using Shift Registers. (A Register in which data gets shifted towards left or right when clock pulses are applied is known as a Shift Register.)

Description : Define synchronous sequential circuit

Last Answer : In synchronous sequential circuits, signals can affect the memory elements only at discrete instant of time.

Description : A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns each. The maximum possible time required for change of state will be (A) 15 ns. (B) 30 ns. (C) 45 ns. (D) 60 ns.

Last Answer : Ans: A 15 ns because in synchronous counter all the flip-flops change state at the same time.

Description : The output of SR flip flop when S=1, R=0 is (A) 1 (B) 0 (C) No change (D) High impedance

Last Answer : Ans: A As for the SR flip-flop S=set input R=reset input ,when S=1, R=0, Flip-flop will be set.

Description : How many two input AND gates and two input OR gates are required to realize Y = BD+CE+AB (A) 1, 1 (B) 4, 2 (C) 3, 2 (D) 2, 3

Last Answer : Ans: A There are three product terms, so three AND gates of two inputs are required. As only two input OR gates are available, so two OR gates are required to get the logical sum of three product terms.

Description : An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the input signal which can be used for proper operation of the counter is approximately (A) 1 MHz. (B) 500 MHz. (C) 2 MHz. (D) 4 MHz.

Last Answer : Maximum time taken for all flip-flops to stabilize is 75ns x 8 + 50 = 650ns. Frequency of operation must be less than 1/650ns = 1.5 MHz.

Description : How many two-input AND and OR gates are required to realize Y=CD+EF+G (A) 2,2. (B) 2,3. (C) 3,3. (D) none of these.

Last Answer : Ans: A Y=CD+EF+G Number of two input AND gates=2 Number of two input OR gates = 2 One OR gate to OR CD and EF and next to OR of G & output of first OR gate.

Description : The commercially available 8-input multiplexer integrated circuit in the TTL family is (A) 7495. (B) 74153. (C) 74154. (D) 74151.

Last Answer : Ans: B MUX integrated circuit in TTL is 74153.

Description : If the inputs to the diagram shown in the illustration were J=1, K=0, H=0, L=1, M=1, what logic levels would be indicated at points 'X' and 'Y' respectively? EL-0089 A. 0,0 B. 0,1 C. 1,0 D. 1,1

Last Answer : Answer: D

Description : If the inputs to the diagram shown in the illustration were J=1, K=1, H=0, L=1, M=1, what logic levels would be indicated at points 'X' and 'Y' respectively? EL-0089 A. 0,0 B. 0,1 C. 1,0 D. 1,1

Last Answer : Answer: D

Description : If the inputs to the diagram shown in the illustration were J=0, K=0, H=1, L=0, M=1, what logic levels would be indicated at points 'X' and 'Y' respectively? EL-0089 A. 0,0 B. 0,1 C. 1,0 D. 1,1

Last Answer : Answer: C

Description : If the inputs to the diagram shown in the illustration were J=1, K=0, H=1, L=1, M=0, what logic levels would be indicated at points 'X' and 'Y' respectively? EL-0089 A. 0,0 B. 0,1 C. 1,0 D. 1,1

Last Answer : Answer: A

Description : How many address bits are required to represent a 32 K memory (A) 10 bits. (B) 12 bits. (C) 14 bits. (D) 16 bits.

Last Answer : (D) 16 bits.

Description : Which TTL logic gate is used for wired ANDing (A) Open collector output (B) Totem Pole (C) Tri state output (D) ECL gates

Last Answer : Ans: A Open collector output.

Description : State function of preset and clear in flip flop.

Last Answer : In the flip flop , when the power is switched on, the state of the circuit is uncertain i.e. may be Q = 1 or Q = 0.  Hence, the function of preset is to set a flip flop i.e. Q = 1 and the function of clear is to clear a flip flop i.e. Q = 0.

Description : In______ transmission, wesend1 start bit (0) at thebeginningand 1 or more stop bits (1s) at the end of each byte. A) synchronous B) asynchronous C) isochronous D) none of the above

Last Answer : asynchronous

Description : What two inputs to a J-K FF will override the other inputs?

Last Answer : Clear (CLR) and preset (PS or PR).

Description : Production function relates - (1) Cost to output (2) Cost to input (3) Wages to profit (4) Inputs to output

Last Answer : (4) Inputs to output Explanation: Production function specifies the output of a firm, an industry, or an entire economy for all combinations of inputs. The relationship of output to inputs is ... relates physical inputs to physical outputs, and prices and costs are not reflected in the function.

Description : A two-input X-OR gate will produce a HIGH output when the inputs are at what logic levels?

Last Answer : . One or the other of the inputs must be HIGH, but not both at the same time.

Description : What is the output Boolean expression for an AND gate with A and B as inputs when the B input is inverted?

Last Answer : AB

Description : A 4-input neuron has weights 1, 2, 3 and 4. The transfer function is linear with the constant of proportionality being equal to 2. The inputs are 4, 10, 5 and 20 respectively. The output will be: a) 238 b) 76 c) 119 d) 123

Last Answer : a) 238

Description : The output of two inputs OR gate is zero only when: (a) Both are one (b) Both are zero (c) Either input is 1 (d) None

Last Answer : (b) Both are zero

Description : In a certain electronic circuit the output is positive if input 1 is positive and input 2 is zero. If both inputs are positive the output is zero. This is: w) an AND circuit x) a NOR circuit y) an OR circuit z) a high-pass filter

Last Answer : ANSWER: Y -- AN OR CIRCUIT

Description : An artificial neurons receives n inputs x1, x2,...,xn with weights w1,w2,...,wn attached to the input links. The weighted sum ............... is computed to be passed on to a non-linear filter ϕ called activation function to release the output. (A) Σ wi (B) Σ xi (C) Σ wi + Σ xi (D) Σ wi . Σ xi

Last Answer : (D) Σ wi . Σ xi

Description : Production function relates (1) Cost to output (2) Cost to input (3) Wages to profit (4) Inputs to output

Last Answer : Inputs to output

Description : List typical inputs and outputs for PLC (four input and any four output).

Last Answer : Typical PLC inputs  Push Button  Selector Switch  Proximity switch  FOOT switch, level switch  Analog input  Typical PLC outputs  Contactor Coil, solenoid, relay  Indicating Lamp  Buzzer  Alaram annunciator