The MSI chip 7474 is
(A) Dual edge triggered JK flip-flop (TTL).
(B) Dual edge triggered D flip-flop (CMOS).
(C) Dual edge triggered D flip-flop (TTL).
(D) Dual edge triggered JK flip-flop (CMOS).

1 Answer

Answer :

Ans: C
 MSI chip 7474 dual edge triggered D Flip-Flop.

Related questions

Description : What is edge-triggered flip-flop?

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Description : In a positive-edge-triggered JK flip-flop, if J and K both are high then the output will be ............. on the rising edge of the clock. (A) No change (B) Set (C) Reset (D) Toggle

Last Answer : (D) Toggle 

Description : In a positive edge triggered JK flip-flop, J = 1, K = 0 and clock pulse is rising, Q will be (a) 0 (b) 1 (c) showing no change (d) toggle 

Last Answer : In a positive edge triggered JK flip-flop, J =1, K= 0 and clock pulse is rising, a Q will be 1

Description : What is the operation of JK flip-flop?

Last Answer : When K input is low and J input is high the Q output of flip-flop is set. When K input is high and J input is low the Q output of flip-flop is reset. When both the inputs ... are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.

Description : For JK flip flop with J=1, K=0, the output after clock pulse will be (A) 0. (B) 1. (C) high impedance. (D) no change.

Last Answer : (B) 1.

Description : Which of following consume minimum power (A) TTL. (B) CMOS. (C) DTL. (D) RTL.

Last Answer : Ans: B CMOS consumes minimum power as in CMOS one p-MOS & one n-MOS transistors are connected in complimentary mode, such that one device is ON & one is OFF.

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Last Answer : (A) ECL

Description : CMOS circuits consume power (A) Equal to TTL (B) Less than TTL (C) Twice of TTL (D) Thrice of TTL

Last Answer : Ans: B As in CMOS one device is ON & one is Always OFF so power consumption is low.

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Last Answer : Ans: A The digital logic family which has the lowest propagation delay time is ECL (Lowest propagation delay time is possible in ECL because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated).

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Last Answer : Ans: B ECL is the fastest logic family of all logic families. (High speeds are possible in ECL because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated.

Description : The digital logic family which has minimum power dissipation is (A) TTL (B) RTL (C) DTL (D) CMOS

Last Answer : (D) CMOS The digital logic family which has minimum power dissipation is CMOS. (CMOS being an unipolar logic family, occupy a very small fraction of silicon Chip area)

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Last Answer : a. Flip-flop

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Description : The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in figure is 10 KHZ. The frequency of the signal at Q is A) 10 KHz B) 2.5 KHz C) 20 KHz D) 5 KHz

Last Answer : The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in figure is 10 KHZ. The frequency of the signal at Q is 5 KHz

Description : Which of the following describes the operation of a positive edge - triggered D -type flip-flop? a) if both inputs are HIGH, the output will toggle b) the output will follow the input on the leading ... on the leading edge of the clock and is passed to the output on the trailing edge of the clock.

Last Answer : Which of the following describes the operation of a positive edge - triggered D -type flip-flop?   the output will follow the input on the leading edge of the clock

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Last Answer : Ans: C Because CMOS circuits have large packing density.

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Last Answer : A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.

Description : What is the operation of T flip-flop?

Last Answer : T flip-flop is also known as Toggle flip-flop. • When T=0 there is no change in the output. • When T=1 the output switch to the complement state (ie) the output toggles.

Description : What is the operation of D flip-flop?

Last Answer : In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.

Description : What are the different types of flip-flop?

Last Answer : There are various types of flip flops. Some of them are mentioned below they are, RS flip-flop SR flip-flop D flip-flop JK flip-flop T flip-flop

Description : Define Flip flop.

Last Answer : The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state.

Description : An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the input signal which can be used for proper operation of the counter is approximately (A) 1 MHz. (B) 500 MHz. (C) 2 MHz. (D) 4 MHz.

Last Answer : Maximum time taken for all flip-flops to stabilize is 75ns x 8 + 50 = 650ns. Frequency of operation must be less than 1/650ns = 1.5 MHz.

Description : The output of SR flip flop when S=1, R=0 is (A) 1 (B) 0 (C) No change (D) High impedance

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Last Answer : (A) D Flip Flop

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Description : Which of the following flip-flops is free from race condition ? (A) T flip-flop (B) SR flip-flop (C) Master-slave JK flip-flop (D) None of the above

Last Answer : (C) Master-slave JK flip-flop

Description : What is race around condition in JK flip flop and how it can be eliminated?

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Description : Read the following statements: i. Gate is a combinational logic. ii. JK Flip-flop in toggle mode is not combinational logic. iii. MSJK Flip-flop suffers from race-around. iv. Counters are sequential circuits. Which choice is correct? (A) i, ii (B) i, ii, iv (C) ii, iii, iv (D) i, ii, iii

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