A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns each. The
maximum possible time required for change of state will be
(A) 15 ns. (B) 30 ns.
(C) 45 ns. (D) 60 ns.

2 Answers

Answer :

(A) 15 ns.

Answer :

Ans: A
 15 ns because in synchronous counter all the flip-flops change state at the same time.

Related questions

Description : An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the input signal which can be used for proper operation of the counter is approximately (A) 1 MHz. (B) 500 MHz. (C) 2 MHz. (D) 4 MHz.

Last Answer : Maximum time taken for all flip-flops to stabilize is 75ns x 8 + 50 = 650ns. Frequency of operation must be less than 1/650ns = 1.5 MHz.

Description : How many flip-flops are required to construct mod 30 counter (A) 5 (B) 6 (C) 4 (D) 8

Last Answer : (A) 5

Description : How many flip flops are required to construct a decade counter (A) 10 (B) 3 (C) 4 (D) 2

Last Answer : Ans: C Decade counter counts 10 states from 0 to 9 ( i.e. from 0000 to 1001 ) Thus four FlipFlop's are required.

Description : How many Flip-Flops are required for mod–16 counter? (A) 5 (B) 6 (C) 3 (D) 4

Last Answer : (D) 4

Description : A ring counter consisting of five Flip-Flops will have (A) 5 states (B) 10 states (C) 32 states (D) Infinite states.

Last Answer : Ans: A A ring counter consisting of Five Flip-Flops will have 5 states.

Description : The number of flip flops contained in IC 7490 is (A) 2. (B) 3. (C) 4. (D) 10.

Last Answer : (A) 2.

Description : Each flip-flop in a 4-bit ripple counter introduces a maximum delay of 40 n sec. The maximum clock frequency is (a) 2.65 MHz (b) 6.25 MHz (c) 5.26 MHz (d) 6.52 MHz 

Last Answer : Each flip-flop in a 4-bit ripple counter introduces a maximum delay of 40 ns. The maximum clock frequency is 6.25MHz. nff  * Tdelay = 4*40 =160ns so, max. frequency = 1/ (200*10-9 ) = 6.25MHz          

Description : The digital logic family which has the lowest propagation delay time is (A) ECL (B) TTL (C) CMOS (D) PMOS

Last Answer : Ans: A The digital logic family which has the lowest propagation delay time is ECL (Lowest propagation delay time is possible in ECL because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated).

Description : In digital ICs, Schottky transistors are preferred over normal transistors because of their (A) Lower Propagation delay. (B) Higher Propagation delay. (C) Lower Power dissipation. (D) Higher Power dissipation.

Last Answer : Ans: A Lower propagation delay as shottky transistors reduce the storage time delay by preventing the transistor from going deep into saturation.

Description : A 3 -stage ripple counter has Flip Flop with propagation delay of 25 nsec and pulse width of strobe input 10 nsec. Then the maximum operating frequency at which counter operates reliably is

Last Answer : A 3 -stage ripple counter has Flip Flop with propagation delay of 25 nsec and pulse width of strobe input 10 nsec. Then the maximum operating frequency at which counter operates reliably is 12.67 MHz

Description : The device which changes from serial data to parallel data is (A) COUNTER (B) MULTIPLEXER (C) DEMULTIPLEXER (D) FLIP-FLOP

Last Answer : Ans: C The device which changes from serial data to parallel data is demultiplexer. (A demultiplexer takes in data from one line and directs it to any of its N outputs depending on the status of the select inputs.)

Description : The number of flip-flops required to design a modulo-272 counter is: (A) 8 (B) 9 (C) 27 (D) 11

Last Answer : 9

Description : Define modulus of a counter. Write the numbers of flip flops required for Mod-6 counter.

Last Answer : Modulus of counter is defined as number of states/clock the counter countes. The numbers of flip flops required for Mod-6 counter is 3.

Description : How many flip-flops are required to build a binary counter circuit to count from 0 to 1023 ? (a) 1 (b) 6 (c) 10 (d) 23 

Last Answer : (c)10

Description : What is modulus of counter? Show the method to determine the no. of flip flops for a mod-52 counter.

Last Answer : Modulus of a counter is the no. of different states through which the counter progress during its operation. It indicates the no. of states in the counter; pulses to be counted are applied to counter. The ... to its starting state after counting N pluses in the case of modulus N counter.

Description : No. of flip-flops used in decade counter (a) 3 (b) 2 (c) 4 (d) None of these

Last Answer : 4

Description : The output of SR flip flop when S=1, R=0 is (A) 1 (B) 0 (C) No change (D) High impedance

Last Answer : Ans: A As for the SR flip-flop S=set input R=reset input ,when S=1, R=0, Flip-flop will be set.

Description : For JK flip flop with J=1, K=0, the output after clock pulse will be (A) 0. (B) 1. (C) high impedance. (D) no change.

Last Answer : (B) 1.

Description : The speed of conversion is maximum in (A) Successive-approximation A/D converter. (B) Parallel-comparative A/D converter. (C) Counter ramp A/D converter. (D) Dual-slope A/D converter.

Last Answer : Ans: B The speed of conversion is maximum in Parallel-comparator A/D converter (Speed of conversion is maximum because the comparisons of the input voltage are carried out simultaneously.)

Description : What are digital elctronic flip flops, State the different types of flip flop and their uses.

Last Answer : Ans-digital electronic flip flops are temporary single bit storage devices.different types of flip flops are JK f/f RS f/f T F/F D f/f this flip flops are using as storage device delay purpose as counter for toggled as shift register etc

Description : What are digital elctronic flip flops, State the different types of flip flop and their uses.

Last Answer : Ans-Digital electronic flip flops are temporary single bit storage devices. Different types of flip flops are JK f/f RS f/f T F/F D f/f this flip flops are using as storage device delay purpose as counter for toggled as shift register etc

Description : What is a master-slave flip-flop?

Last Answer : A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.

Description : What is edge-triggered flip-flop?

Last Answer : The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive ... negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock.

Description : What is the operation of T flip-flop?

Last Answer : T flip-flop is also known as Toggle flip-flop. • When T=0 there is no change in the output. • When T=1 the output switch to the complement state (ie) the output toggles.

Description : What is the operation of JK flip-flop?

Last Answer : When K input is low and J input is high the Q output of flip-flop is set. When K input is high and J input is low the Q output of flip-flop is reset. When both the inputs ... are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.

Description : What is the operation of D flip-flop?

Last Answer : In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.

Description : What are the different types of flip-flop?

Last Answer : There are various types of flip flops. Some of them are mentioned below they are, RS flip-flop SR flip-flop D flip-flop JK flip-flop T flip-flop

Description : Define Flip flop.

Last Answer : The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state.

Description : The MSI chip 7474 is (A) Dual edge triggered JK flip-flop (TTL). (B) Dual edge triggered D flip-flop (CMOS). (C) Dual edge triggered D flip-flop (TTL). (D) Dual edge triggered JK flip-flop (CMOS).

Last Answer : Ans: C MSI chip 7474 dual edge triggered D Flip-Flop.

Description : Define synchronous sequential circuit

Last Answer : In synchronous sequential circuits, signals can affect the memory elements only at discrete instant of time.

Description : The output of a JK flipflop with asynchronous preset and clear inputs is 1'. The output can be changed to 0' with one of the following conditions. (A) By applying J = 0, K = 0 and using a clock. (B) ... (C) By applying J = 1, K = 1 and using the clock. (D) By applying a synchronous preset input.

Last Answer : Ans: C Preset state of JK Flip-Flop =1 With J=1 K=1 and the clock next state will be complement of the present state.

Description : The A/D converter whose conversion time is independent of the number of bits is (A) Dual slope (B) Counter type (C) Parallel conversion (D) Successive approximation.

Last Answer : Ans: C The A/D converter whose conversion time is independent of the Number of bits is Parallel conversion. (This type uses an array of comparators connected in parallel and comparators compare the input voltage at a particular ratio of the reference voltage).

Description : Suppose that the one-way propagation delay for a 100 Mbps Ethernet having 48-bit jamming signal is 1.04 micro-seconds. The minimum frame size in bits is: a. 112 b. 160 c. 208 d. 256

Last Answer : d. 256

Description : Suppose the round trip propagation delay for a 10 Mbps Ethernet having 48-bit jamming signal is 46.4 ms. The minimum frame size is a. 94 b. 416 c. 464

Last Answer : c. 464

Description : In a token ring network the transmission speed is 10^7 bps and the propagation speed is 200 metres/micro second. The 1- bit delay in this network is equivalent to: a. 500 metres of cable. b. 200 metres of cable. c. 20 metres of cable. d. 50 metres of cable

Last Answer : c. 20 metres of cable.

Description : Shifting a register content to left by one bit position is equivalent to (A) division by two. (B) addition by two. (C) multiplication by two. (D) subtraction by two

Last Answer : (C) multiplication by two.

Description : 1’s complement representation of decimal number of -17 by using 8 bit representation is (A) 1110 1110 (B) 1101 1101 (C) 1100 1100 (D) 0001 0001

Last Answer : (A) 1110 1110

Description : The code where all successive numbers differ from their preceding number by single bit is (A) Binary code. (B) BCD. (C) Excess – 3. (D) Gray.

Last Answer : Ans: D The code where all successive numbers differ from their preceding number by single bit is Gray Code. (It is an unweighted code. The most important characteristic of this code is that only a single bit change occurs when going from one code number to next.)

Description : Convert decimal 20 to octal. 45) A) 168 B) 108 C) 188 D) 248

Last Answer : D) 248

Description : What is the time delay introduced by a 75-ft coaxial cable with a dielectric constant of 2.3? A. 1.54 ns B. 11.5 ns C. 115.6 ns D. 1156 ns

Last Answer : C. 115.6 ns

Description : What is transit time (time delay) of a 50-ft length transmission line of the above problem? A. 50 ns B. 100 ns C. 75 ns D. 65 ns

Last Answer : C. 75 ns

Description : A sender uses the Stop-and-Wait ARQ protocol for reliable transmission of frames. Frames are of size 1000 bytes and the transmission rate at the sender is 80 Kbps (1Kbps = 1000 bits/second). Size of ... is lost, the sender throughput is __________ bytes/second. a. 2500 b. 2000 c. 1500 d. 500

Last Answer : a. 2500

Description : the number of columns in a state table for a sequential circuit with m flip-flops and n inputs is.

Last Answer : Ans-Its 2m+2n because.. If there are m flip-flops there should be 2m nodes. If there are n inputs then each node will have 2n.

Description : The hexadecimal equivalent of decimal 60 is ________. 70) A) 3C16 B) 3D16 C) 4D16 D) 5C16

Last Answer : A) 3C16

Description : The BCD equivalent of decimal 912 is ________. 60) A) 1001 0001 0010BCD B) 1001 1000 0001BCD C) 0111 1111 1110BCD D) 0010 001 1001BCD

Last Answer : A) 1001 0001 0010BCD

Last Answer : A 12 bit counter type A/D converter uses a 1 MHz clock. Its maximum conversion time is 4096μs.

Description : Why do so many people have cracked heels plus, due to wearing flip flops?

Last Answer : How do you know this is caused from flip flops?

Description : When and how is it acceptable for an adult male to wear socks with sandals/flip flops?

Last Answer : Whenever the hell he wants. Unless he is severely mentally deficient, he had some idea of how he will be viewed and judged by some, and so makes decisions with full awareness of potential social consequences. ;-)

Description : Why don't you ever see athletes wearing flip flops when they compete?

Last Answer : answer:Because it would be bloody stupid Your next question must be, “but why is it stupid?” Comfort Power Performance enhancing Injury prevention

Description : Can someone explain to me why so many flip-flops are being made with ridges and bumps?

Last Answer : Probably grip/airflow for the soles of your feet.