Description : Convert the decimal number 0.0625 to binary. 100) A) 0000.0111 B) 0000.1110 C) 0000.0011 D) 0000.0001
Last Answer : D) 0000.0001
Description : The decimal equivalent of the BCD value 0111 0110 1000 is ________. 124) A) 70810 B) 17210 C) 76810 D) 6871
Last Answer : C) 76810
Description : The BCD equivalent of decimal 64 is ________. 101) A) 0111 0110BCD B) 0111 1110BCD C) 0100 0010BCD D) 0110 0100BCD
Last Answer : D) 0110 0100BCD
Description : Convert the decimal number 14.875 to binary. 87) A) 1110.0111 B) 1110.1110 C) 1111.1011 D) 1100.1100
Last Answer : B) 1110.1110
Description : The BCD equivalent of decimal 912 is ________. 60) A) 1001 0001 0010BCD B) 1001 1000 0001BCD C) 0111 1111 1110BCD D) 0010 001 1001BCD
Last Answer : A) 1001 0001 0010BCD
Description : Convert the decimal number 6.75 to binary. 14) A) 0110.1100 B) 0111.1100 C) 0110.0110 D) 0110.1010
Last Answer : A) 0110.1100
Description : The output of a JK flipflop with asynchronous preset and clear inputs is 1'. The output can be changed to 0' with one of the following conditions. (A) By applying J = 0, K = 0 and using a clock. (B) ... (C) By applying J = 1, K = 1 and using the clock. (D) By applying a synchronous preset input.
Last Answer : Ans: C Preset state of JK Flip-Flop =1 With J=1 K=1 and the clock next state will be complement of the present state.
Description : When an input signal A=11001 is applied to a NOT gate serially, its output signal is (A) 00111. (B) 00110. (C) 10101. (D) 11001.
Last Answer : When an input signal A=01001 is applied to a NOT gate serially , it's output signal is
Description : In successive-approximation A/D converter, offset voltage equal to 1/2 LSB is added to the D/A converter's output. This is done to (A) Improve the speed of operation. (B) Reduce the maximum ... Increase the number of bits at the output. (D) Increase the range of input voltage that can be converted
Last Answer : (B) Reduce the maximum quantization error.
Description : If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is (A) 1000 Hz (B) 500 Hz (C) 333 Hz (D) 12.5 Hz.
Last Answer : (D) 12.5 Hz.
Description : For JK flipflop J = 0, K=1, the output after clock pulse will be (A) 1. (B) no change. (C) 0. (D) high impedance.
Last Answer : Ans: C J=0, K=1, these inputs will reset the flip-flop after the clock pulse. So whatever be the previous output, the next state will be 0.
Description : The output of SR flip flop when S=1, R=0 is (A) 1 (B) 0 (C) No change (D) High impedance
Last Answer : Ans: A As for the SR flip-flop S=set input R=reset input ,when S=1, R=0, Flip-flop will be set.
Description : For JK flip flop with J=1, K=0, the output after clock pulse will be (A) 0. (B) 1. (C) high impedance. (D) no change.
Last Answer : (B) 1.
Description : The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either (A) a NAND or an EX-OR (B) an OR or an EX-NOR (C) an AND or an EX-OR (D) a NOR or an EX-NOR
Last Answer : (D) a NOR or an EX-NOR
Description : How many two input AND gates and two input OR gates are required to realize Y = BD+CE+AB (A) 1, 1 (B) 4, 2 (C) 3, 2 (D) 2, 3
Last Answer : Ans: A There are three product terms, so three AND gates of two inputs are required. As only two input OR gates are available, so two OR gates are required to get the logical sum of three product terms.
Description : An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the input signal which can be used for proper operation of the counter is approximately (A) 1 MHz. (B) 500 MHz. (C) 2 MHz. (D) 4 MHz.
Last Answer : Maximum time taken for all flip-flops to stabilize is 75ns x 8 + 50 = 650ns. Frequency of operation must be less than 1/650ns = 1.5 MHz.
Description : How many two-input AND and OR gates are required to realize Y=CD+EF+G (A) 2,2. (B) 2,3. (C) 3,3. (D) none of these.
Last Answer : Ans: A Y=CD+EF+G Number of two input AND gates=2 Number of two input OR gates = 2 One OR gate to OR CD and EF and next to OR of G & output of first OR gate.
Description : The commercially available 8-input multiplexer integrated circuit in the TTL family is (A) 7495. (B) 74153. (C) 74154. (D) 74151.
Last Answer : Ans: B MUX integrated circuit in TTL is 74153.
Description : A full adder logic circuit will have (A) Two inputs and one output. (B) Three inputs and three outputs. (C) Two inputs and two outputs. (D) Three inputs and two outputs.
Last Answer : Ans: D A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there.
Description : The NOR gate output will be low if the two inputs are (A) 00 (B) 01 (C) 10 (D) 11
Last Answer : A
Description : Which TTL logic gate is used for wired ANDing (A) Open collector output (B) Totem Pole (C) Tri state output (D) ECL gates
Last Answer : Ans: A Open collector output.
Description : The NAND gate output will be low if the two inputs are (A) 00 (B) 01 (C) 10 (D) 11
Last Answer : (D) 11
Description : The input hexadecimal representation of 1110 is _______________ a) 0111 b) E c) 15 d) 14
Last Answer : Answer: b Explanation: In hexadecimal number system, 1110 = 15, which is represented by the alphabet E. Some representations are: A 10 B 11 C 12 D 13 E 14 F 15
Description : The process of entering data into a ROM is called (A) burning in the ROM (B) programming the ROM (C) changing the ROM (D) charging the ROM
Last Answer : Ans: B The process of entering data into ROM is known as programming the ROM.
Description : The device which changes from serial data to parallel data is (A) COUNTER (B) MULTIPLEXER (C) DEMULTIPLEXER (D) FLIP-FLOP
Last Answer : Ans: C The device which changes from serial data to parallel data is demultiplexer. (A demultiplexer takes in data from one line and directs it to any of its N outputs depending on the status of the select inputs.)
Description : Data can be changed from special code to temporal code by using (A) Shift registers (B) counters (C) Combinational circuits (D) A/D converters.
Last Answer : Ans: A Data can be changed from special code to temporal code by using Shift Registers. (A Register in which data gets shifted towards left or right when clock pulses are applied is known as a Shift Register.)
Description : What is used to identify whether a data word has an odd or even number of 1’s ? (1) Carry bit (2) Sign bit (3) Zero bit (4) Parity bit
Last Answer : Parity bit
Description : What is the decimal value of 20? 127) A) 2 B) 0 C) 1 D) 3
Last Answer : C) 1
Description : What is the decimal value of 2-3? 74) A) 0.25 B) 0.75 C) 0.125 D) 0.8
Last Answer : C) 0.125
Description : Which binary value equals 2-1? 61) A) 1.0000 B) 0.0010 C) 0.0001 D) 0.1000
Last Answer : D) 0.1000
Description : What numeric symbols are used in the binary number system? 58) A) 0 through 8 B) 0, 1, 2 C) 1, 2 D) 0, 1
Last Answer : D) 0, 1
Description : What is the decimal value of 2 1? 35) A) 1 B) 4 C) 2 D) 0
Last Answer : C) 2
Last Answer : C) 8716
Description : What is the decimal value of 2-1? 33) A) 0.1 B) 0.25 C) 0.5 D) 0.05
Last Answer : C) 0.5
Description : What is the decimal value of 2-2? 11) A) 0.5 B) 0.125 C) 0.2 D) 0.25
Last Answer : D) 0.25
Description : Convert the binary number 0000.1010 to decimal. 6) A) 0.10 B) 0.55 C) 0.50 D) 0.625
Last Answer : D) 0.625
Description : The logic 0 level of a CMOS logic device is approximately (A) 1.2 volts (B) 0.4 volts (C) 5 volts (D) 0 volts
Last Answer : Ans: D CMOS logic low level is 0 volts approx.
Description : he building block of a parity or BCC generator is _____
Last Answer : XOR
Description : For the 8-bit word 00111001, the check bits stored with it would be 0111. Suppose when the word is read from memory, the check bits are calculated to be 1101. What is the data word that was read from memory? (A) 10011001 (B) 00011001 (C) 00111000 (D) 11000110
Last Answer : (B) 00011001
Description : Define Asynchronous sequential circuit?
Last Answer : In asynchronous sequential circuits change in input signals can affect memory element at any instant of time.
Description : Define synchronous sequential circuit
Last Answer : In synchronous sequential circuits, signals can affect the memory elements only at discrete instant of time.
Description : What are the different types of shift type?
Last Answer : There are five types. They are, Serial In Serial Out Shift Register Serial In Parallel Out Shift Register Parallel In Serial Out Shift Register Parallel In Parallel Out Shift Register Bidirectional Shift Register
Description : Define shift registers.
Last Answer : The binary information in a register can be moved from stage to stage within the register or into or out of the register upon application of clock ... arithmetic and logic operations used in microprocessors. This gives rise to group of registers called shift registers.
Description : Define registers.
Last Answer : A register is a group of flip-flops flip-flop can store one bit information. So an n-bit register has a group of n flip-flops and is capable of storing any binary information/number containing n-bits.
Description : What is a master-slave flip-flop?
Last Answer : A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.
Description : What is edge-triggered flip-flop?
Last Answer : The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive ... negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock.
Description : Define race around condition.
Last Answer : In JK flip-flop output is fed back to the input. Therefore change in the output results change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition iscalled ‘race around condition’.
Description : What is the operation of T flip-flop?
Last Answer : T flip-flop is also known as Toggle flip-flop. • When T=0 there is no change in the output. • When T=1 the output switch to the complement state (ie) the output toggles.
Description : What is the operation of JK flip-flop?
Last Answer : When K input is low and J input is high the Q output of flip-flop is set. When K input is high and J input is low the Q output of flip-flop is reset. When both the inputs ... are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.
Description : What is the operation of D flip-flop?
Last Answer : In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.